diff --git a/wally-pipelined/regression/wally-coremark_bare.do b/wally-pipelined/regression/wally-coremark_bare.do
index fdb40a05..421ef6d5 100644
--- a/wally-pipelined/regression/wally-coremark_bare.do
+++ b/wally-pipelined/regression/wally-coremark_bare.do
@@ -93,7 +93,7 @@ add wave -divider RAM
 add wave -hex -r /testbench/dut/uncore/dtim/RAM
 add wave -divider Misc
 add wave -divider
-#add wave -hex -r /testbench/*
+add wave -hex -r /testbench/*
 
 -- Set Wave Output Items 
 TreeUpdate [SetDefaultTree]
@@ -111,5 +111,6 @@ set DefaultRadix hexadecimal
 -- Run the Simulation 
 #run 7402000
 #run 12750
-run -all
+#run -all
+run 3000
 #quit
diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv
index 529a6b98..b21772e2 100644
--- a/wally-pipelined/testbench/testbench-coremark_bare.sv
+++ b/wally-pipelined/testbench/testbench-coremark_bare.sv
@@ -91,6 +91,12 @@ module testbench();
         $stop;
       end
     end
+
+  initial begin
+    $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.DirPredictor.memory.memory);
+    $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory);
+  end
+
    
 endmodule
 /* verilator lint_on STMTDLY */