forked from Github_Repos/cvw
added missing files
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@ -31,6 +31,7 @@ module cvtshiftcalc(
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// | `NF-1 zeros | Mantissa | 0's if nessisary |
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// | `NF-1 zeros | Mantissa | 0's if nessisary |
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// - otherwise:
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// - otherwise:
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// | LzcInM | 0's if nessisary |
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// | LzcInM | 0's if nessisary |
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// change to int shift to the left one
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assign CvtShiftIn = ToInt ? {{`XLEN{1'b0}}, XManM[`NF]&~CvtCalcExpM[`NE], XManM[`NF-1]|(CvtCalcExpM[`NE]&XManM[`NF]), XManM[`NF-2:0], {`CVTLEN-`XLEN{1'b0}}} :
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assign CvtShiftIn = ToInt ? {{`XLEN{1'b0}}, XManM[`NF]&~CvtCalcExpM[`NE], XManM[`NF-1]|(CvtCalcExpM[`NE]&XManM[`NF]), XManM[`NF-2:0], {`CVTLEN-`XLEN{1'b0}}} :
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CvtResDenormUfM ? {{`NF-1{1'b0}}, XManM, {`CVTLEN-`NF+1{1'b0}}} :
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CvtResDenormUfM ? {{`NF-1{1'b0}}, XManM, {`CVTLEN-`NF+1{1'b0}}} :
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{CvtLzcInM, {`NF+1{1'b0}}};
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{CvtLzcInM, {`NF+1{1'b0}}};
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@ -179,7 +179,7 @@ module fcvt (
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// - shifted right by XLEN (XLEN)
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// - shifted right by XLEN (XLEN)
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// - shift left to normilize (-1-ZeroCnt)
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// - shift left to normilize (-1-ZeroCnt)
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// - newBias to make the biased exponent
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// - newBias to make the biased exponent
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//
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// oldexp - biasold +newbias - (ZeroCnt+1)&(XDenormE|IntToFp)
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assign CvtCalcExpE = {1'b0, OldExp} - (`NE+1)'(`BIAS) + {2'b0, NewBias} - {{`NE{1'b0}}, XDenormE|IntToFp} - {{`NE-`LOGCVTLEN+1{1'b0}}, (ZeroCnt&{`LOGCVTLEN{XDenormE|IntToFp}})};
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assign CvtCalcExpE = {1'b0, OldExp} - (`NE+1)'(`BIAS) + {2'b0, NewBias} - {{`NE{1'b0}}, XDenormE|IntToFp} - {{`NE-`LOGCVTLEN+1{1'b0}}, (ZeroCnt&{`LOGCVTLEN{XDenormE|IntToFp}})};
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// find if the result is dnormal or underflows
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// find if the result is dnormal or underflows
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// - if Calculated expoenent is 0 or negitive (and the input/result is not exactaly 0)
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// - if Calculated expoenent is 0 or negitive (and the input/result is not exactaly 0)
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20
pipelined/src/fpu/negateintres.sv
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20
pipelined/src/fpu/negateintres.sv
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@ -0,0 +1,20 @@
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`include "wally-config.vh"
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module negateintres(
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input logic XSgnM,
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input logic [`NORMSHIFTSZ-1:0] Shifted,
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input logic Signed,
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input logic Int64,
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input logic Plus1,
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output logic [1:0] NegResMSBS,
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output logic [`XLEN+1:0] NegRes
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);
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// round and negate the positive res if needed
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assign NegRes = XSgnM ? -({2'b0, Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`XLEN]}+{{`XLEN+1{1'b0}}, Plus1}) : {2'b0, Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`XLEN]}+{{`XLEN+1{1'b0}}, Plus1};
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assign NegResMSBS = Signed ? Int64 ? NegRes[`XLEN:`XLEN-1] : NegRes[32:31] :
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Int64 ? NegRes[`XLEN+1:`XLEN] : NegRes[33:32];
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endmodule
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@ -237,7 +237,7 @@ module resultselect(
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// signed | -2^31 | -2^63 |
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// signed | -2^31 | -2^63 |
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// unsigned | 0 | 0 |
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// unsigned | 0 | 0 |
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//
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//
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// - positive infinity and out of range negitive input and NaNs
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// - positive infinity and out of range positive input and NaNs
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// | int | long |
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// | int | long |
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// signed | 2^31-1 | 2^63-1 |
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// signed | 2^31-1 | 2^63-1 |
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// unsigned | 2^32-1 | 2^64-1 |
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// unsigned | 2^32-1 | 2^64-1 |
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32
pipelined/src/fpu/roundsign.sv
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32
pipelined/src/fpu/roundsign.sv
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@ -0,0 +1,32 @@
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`include "wally-config.vh"
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module roundsign(
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input logic PSgnM, ZSgnEffM,
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input logic InvZM,
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input logic XSgnM,
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input logic YSgnM,
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input logic NegSumM,
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input logic FmaOp,
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input logic DivOp,
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input logic CvtOp,
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input logic CvtResSgnM,
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output logic RoundSgn
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);
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logic FmaResSgnTmp;
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logic DivSgn;
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// is the result negitive
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// if p - z is the Sum negitive
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// if -p + z is the Sum positive
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// if -p - z then the Sum is negitive
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assign FmaResSgnTmp = NegSumM^PSgnM; //*** move to execute stage
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// assign FmaResSgnTmp = InvZM&(ZSgnEffM)&NegSumM | InvZM&PSgnM&~NegSumM | (ZSgnEffM&PSgnM);
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assign DivSgn = XSgnM^YSgnM;
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// Sign for rounding calulation
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assign RoundSgn = (FmaResSgnTmp&FmaOp) | (CvtResSgnM&CvtOp) | (DivSgn&DivOp);
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endmodule
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@ -4,12 +4,14 @@ module lzc #(parameter WIDTH = 1) (
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output logic [$clog2(WIDTH+1)-1:0] ZeroCnt
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output logic [$clog2(WIDTH+1)-1:0] ZeroCnt
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);
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);
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/* verilator lint_off CMPCONST */
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/* verilator lint_off CMPCONST */
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/* verilator lint_off WIDTH */
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logic [$clog2(WIDTH+1)-1:0] i;
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int i;
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always_comb begin
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always_comb begin
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i = 0;
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i = 0;
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while (~num[WIDTH-1-(32)'(i)] & $unsigned(i) <= $unsigned(($clog2(WIDTH+1))'(WIDTH-1))) i = i+1; // search for leading one
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while (~num[WIDTH-1-i] & (i < WIDTH)) i = i+1; // search for leading one
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ZeroCnt = i;
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ZeroCnt = i;
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end
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end
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/* verilator lint_on WIDTH */
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/* verilator lint_on CMPCONST */
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/* verilator lint_on CMPCONST */
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endmodule
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endmodule
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@ -641,7 +641,7 @@ module testbenchfp;
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.Xe(XExp), .Ye(YExp), .Ze(ZExp),
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.Xe(XExp), .Ye(YExp), .Ze(ZExp),
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.Xm(XMan), .Ym(YMan), .Zm(ZMan),
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.Xm(XMan), .Ym(YMan), .Zm(ZMan),
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.XZeroE(XZero), .YZeroE(YZero), .ZZeroE(ZZero),
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.XZeroE(XZero), .YZeroE(YZero), .ZZeroE(ZZero),
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.FOpCtrlE(OpCtrlVal), .FmtE(ModFmt), .Sm, .NegSumE, .InvZE, .FmaNormCntE, .ZSgnEffE, .Ps,
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.FOpCtrlE(OpCtrlVal), .FmtE(ModFmt), .Sm, .NegSumE, .InvA(InvZE), .FmaNormCntE, .ZSgnEffE, .Ps,
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.Pe, .AddendStickyE, .KillProdE);
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.Pe, .AddendStickyE, .KillProdE);
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postprocess postprocess(.XSgnM(XSgn), .YSgnM(YSgn), .PostProcSelM(UnitVal[1:0]),
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postprocess postprocess(.XSgnM(XSgn), .YSgnM(YSgn), .PostProcSelM(UnitVal[1:0]),
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@ -818,7 +818,15 @@ end
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// check if result is correct
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// check if result is correct
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// - wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage)
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// - wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage)
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if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&((~DivStart&DivDone)^~(UnitVal == `DIVUNIT))&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin
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if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&((UnitVal !== `DIVUNIT))&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin
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errors += 1;
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$display("There is an error in %s", Tests[TestNum]);
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$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
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$stop;
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end
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// division
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else if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&(~DivStart&DivDone)&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin
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errors += 1;
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errors += 1;
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$display("There is an error in %s", Tests[TestNum]);
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$display("There is an error in %s", Tests[TestNum]);
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$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
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$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
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