From 010a05f58363f77d9fd873b16e5c6df982aa2dbd Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Sun, 3 Jul 2022 21:40:47 -0700 Subject: [PATCH] added missing files --- pipelined/src/fpu/cvtshiftcalc.sv | 1 + pipelined/src/fpu/fcvt.sv | 2 +- pipelined/src/fpu/negateintres.sv | 20 ++++++++++++++++++ pipelined/src/fpu/resultselect.sv | 2 +- pipelined/src/fpu/roundsign.sv | 32 +++++++++++++++++++++++++++++ pipelined/src/generic/lzc.sv | 6 ++++-- pipelined/testbench/testbench-fp.sv | 12 +++++++++-- 7 files changed, 69 insertions(+), 6 deletions(-) create mode 100644 pipelined/src/fpu/negateintres.sv create mode 100644 pipelined/src/fpu/roundsign.sv diff --git a/pipelined/src/fpu/cvtshiftcalc.sv b/pipelined/src/fpu/cvtshiftcalc.sv index ab054342..1c7fbd03 100644 --- a/pipelined/src/fpu/cvtshiftcalc.sv +++ b/pipelined/src/fpu/cvtshiftcalc.sv @@ -31,6 +31,7 @@ module cvtshiftcalc( // | `NF-1 zeros | Mantissa | 0's if nessisary | // - otherwise: // | LzcInM | 0's if nessisary | + // change to int shift to the left one assign CvtShiftIn = ToInt ? {{`XLEN{1'b0}}, XManM[`NF]&~CvtCalcExpM[`NE], XManM[`NF-1]|(CvtCalcExpM[`NE]&XManM[`NF]), XManM[`NF-2:0], {`CVTLEN-`XLEN{1'b0}}} : CvtResDenormUfM ? {{`NF-1{1'b0}}, XManM, {`CVTLEN-`NF+1{1'b0}}} : {CvtLzcInM, {`NF+1{1'b0}}}; diff --git a/pipelined/src/fpu/fcvt.sv b/pipelined/src/fpu/fcvt.sv index 26ca7dd8..20ae1de1 100644 --- a/pipelined/src/fpu/fcvt.sv +++ b/pipelined/src/fpu/fcvt.sv @@ -179,7 +179,7 @@ module fcvt ( // - shifted right by XLEN (XLEN) // - shift left to normilize (-1-ZeroCnt) // - newBias to make the biased exponent - // + // oldexp - biasold +newbias - (ZeroCnt+1)&(XDenormE|IntToFp) assign CvtCalcExpE = {1'b0, OldExp} - (`NE+1)'(`BIAS) + {2'b0, NewBias} - {{`NE{1'b0}}, XDenormE|IntToFp} - {{`NE-`LOGCVTLEN+1{1'b0}}, (ZeroCnt&{`LOGCVTLEN{XDenormE|IntToFp}})}; // find if the result is dnormal or underflows // - if Calculated expoenent is 0 or negitive (and the input/result is not exactaly 0) diff --git a/pipelined/src/fpu/negateintres.sv b/pipelined/src/fpu/negateintres.sv new file mode 100644 index 00000000..2dee1f18 --- /dev/null +++ b/pipelined/src/fpu/negateintres.sv @@ -0,0 +1,20 @@ +`include "wally-config.vh" + +module negateintres( + input logic XSgnM, + input logic [`NORMSHIFTSZ-1:0] Shifted, + input logic Signed, + input logic Int64, + input logic Plus1, + output logic [1:0] NegResMSBS, + output logic [`XLEN+1:0] NegRes +); + + + // round and negate the positive res if needed + assign NegRes = XSgnM ? -({2'b0, Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`XLEN]}+{{`XLEN+1{1'b0}}, Plus1}) : {2'b0, Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`XLEN]}+{{`XLEN+1{1'b0}}, Plus1}; + + assign NegResMSBS = Signed ? Int64 ? NegRes[`XLEN:`XLEN-1] : NegRes[32:31] : + Int64 ? NegRes[`XLEN+1:`XLEN] : NegRes[33:32]; + +endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/resultselect.sv b/pipelined/src/fpu/resultselect.sv index b87c9548..81f6a74d 100644 --- a/pipelined/src/fpu/resultselect.sv +++ b/pipelined/src/fpu/resultselect.sv @@ -237,7 +237,7 @@ module resultselect( // signed | -2^31 | -2^63 | // unsigned | 0 | 0 | // - // - positive infinity and out of range negitive input and NaNs + // - positive infinity and out of range positive input and NaNs // | int | long | // signed | 2^31-1 | 2^63-1 | // unsigned | 2^32-1 | 2^64-1 | diff --git a/pipelined/src/fpu/roundsign.sv b/pipelined/src/fpu/roundsign.sv new file mode 100644 index 00000000..a5a34642 --- /dev/null +++ b/pipelined/src/fpu/roundsign.sv @@ -0,0 +1,32 @@ +`include "wally-config.vh" + +module roundsign( + input logic PSgnM, ZSgnEffM, + input logic InvZM, + input logic XSgnM, + input logic YSgnM, + input logic NegSumM, + input logic FmaOp, + input logic DivOp, + input logic CvtOp, + input logic CvtResSgnM, + output logic RoundSgn +); + + logic FmaResSgnTmp; + logic DivSgn; + + // is the result negitive + // if p - z is the Sum negitive + // if -p + z is the Sum positive + // if -p - z then the Sum is negitive + assign FmaResSgnTmp = NegSumM^PSgnM; //*** move to execute stage + + // assign FmaResSgnTmp = InvZM&(ZSgnEffM)&NegSumM | InvZM&PSgnM&~NegSumM | (ZSgnEffM&PSgnM); + + assign DivSgn = XSgnM^YSgnM; + + // Sign for rounding calulation + assign RoundSgn = (FmaResSgnTmp&FmaOp) | (CvtResSgnM&CvtOp) | (DivSgn&DivOp); + +endmodule \ No newline at end of file diff --git a/pipelined/src/generic/lzc.sv b/pipelined/src/generic/lzc.sv index 123edcb6..9eab5920 100644 --- a/pipelined/src/generic/lzc.sv +++ b/pipelined/src/generic/lzc.sv @@ -4,12 +4,14 @@ module lzc #(parameter WIDTH = 1) ( output logic [$clog2(WIDTH+1)-1:0] ZeroCnt ); /* verilator lint_off CMPCONST */ +/* verilator lint_off WIDTH */ - logic [$clog2(WIDTH+1)-1:0] i; + int i; always_comb begin i = 0; - while (~num[WIDTH-1-(32)'(i)] & $unsigned(i) <= $unsigned(($clog2(WIDTH+1))'(WIDTH-1))) i = i+1; // search for leading one + while (~num[WIDTH-1-i] & (i < WIDTH)) i = i+1; // search for leading one ZeroCnt = i; end +/* verilator lint_on WIDTH */ /* verilator lint_on CMPCONST */ endmodule diff --git a/pipelined/testbench/testbench-fp.sv b/pipelined/testbench/testbench-fp.sv index 1fc35525..cc613e2c 100644 --- a/pipelined/testbench/testbench-fp.sv +++ b/pipelined/testbench/testbench-fp.sv @@ -641,7 +641,7 @@ module testbenchfp; .Xe(XExp), .Ye(YExp), .Ze(ZExp), .Xm(XMan), .Ym(YMan), .Zm(ZMan), .XZeroE(XZero), .YZeroE(YZero), .ZZeroE(ZZero), - .FOpCtrlE(OpCtrlVal), .FmtE(ModFmt), .Sm, .NegSumE, .InvZE, .FmaNormCntE, .ZSgnEffE, .Ps, + .FOpCtrlE(OpCtrlVal), .FmtE(ModFmt), .Sm, .NegSumE, .InvA(InvZE), .FmaNormCntE, .ZSgnEffE, .Ps, .Pe, .AddendStickyE, .KillProdE); postprocess postprocess(.XSgnM(XSgn), .YSgnM(YSgn), .PostProcSelM(UnitVal[1:0]), @@ -818,7 +818,15 @@ end // check if result is correct // - wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage) - if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&((~DivStart&DivDone)^~(UnitVal == `DIVUNIT))&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin + if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&((UnitVal !== `DIVUNIT))&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin + errors += 1; + $display("There is an error in %s", Tests[TestNum]); + $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); + $stop; + end + + // division + else if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&(~DivStart&DivDone)&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin errors += 1; $display("There is an error in %s", Tests[TestNum]); $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);