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Fixed multiplier and pointed arch tests to new path in addins

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This commit is contained in:
David Harris 2021-10-18 15:43:59 -07:00
parent e681020d9e
commit 00d8035836
3 changed files with 7 additions and 9 deletions
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6
wally-pipelined/src/muldiv/mul.sv
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@ -60,10 +60,6 @@ module mul (
// Execute Stage: Compute partial products // Execute Stage: Compute partial products
////////////////////////////// //////////////////////////////
// portions of product
//assign Pprime = {1'b0, SrcAE[`XLEN-2:0]} * {1'b0, SrcBE[`XLEN-2:0]};
// *** assumes unsigned multiplication
assign Aprime = {1'b0, SrcAE[`XLEN-2:0]}; assign Aprime = {1'b0, SrcAE[`XLEN-2:0]};
assign Bprime = {1'b0, SrcBE[`XLEN-2:0]}; assign Bprime = {1'b0, SrcBE[`XLEN-2:0]};
redundantmul #(`XLEN) bigmul(.a(Aprime), .b(Bprime), .out0(PP0E), .out1(PP1E)); redundantmul #(`XLEN) bigmul(.a(Aprime), .b(Bprime), .out0(PP0E), .out1(PP1E));
@ -77,8 +73,6 @@ module mul (
// assign MULHU = (Funct3E == 2'b11); // signal unused // assign MULHU = (Funct3E == 2'b11); // signal unused
// Handle signs // Handle signs
// assign PP0E = 0;
// assign PP1E = Pprime; // same for all flavors
assign PP2E = {2'b00, (MULH | MULHSU) ? ~PA : PA, {(`XLEN-1){1'b0}}}; assign PP2E = {2'b00, (MULH | MULHSU) ? ~PA : PA, {(`XLEN-1){1'b0}}};
assign PP3E = {2'b00, (MULH) ? ~PB : PB, {(`XLEN-1){1'b0}}}; assign PP3E = {2'b00, (MULH) ? ~PB : PB, {(`XLEN-1){1'b0}}};
always_comb always_comb

8
wally-pipelined/src/muldiv/redundantmul.sv
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@ -31,9 +31,13 @@ module redundantmul #(parameter WIDTH =8)(
generate generate
if (`DESIGN_COMPILER == 1) if (`DESIGN_COMPILER == 1)
DW02_multp #(WIDTH, WIDTH, 2*WIDTH) bigmul(.a, .b, .tc(1'b0), .out0, .out1); DW02_multp #(WIDTH, WIDTH, 2*WIDTH) mul(.a, .b, .tc(1'b0), .out0, .out1);
else if (`DESIGN_COMPILER == 2) else if (`DESIGN_COMPILER == 2)
mult_cs #(WIDTH) hackymul (.a, .b, .tc(1'b0), .sum(out0), .carry(out1)); mult_cs #(WIDTH) mul(.a, .b, .tc(1'b0), .sum(out0), .carry(out1));
else begin // force a nonredunant multipler. This will simulate properly and also is appropriate for FPGAs.
assign out0 = a * b;
assign out1 = 0;
end
endgenerate endgenerate
endmodule endmodule

2
wally-pipelined/testbench/tests.vh
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@ -28,7 +28,7 @@
string tvpaths[] = '{ string tvpaths[] = '{
"../../imperas-riscv-tests/work/", "../../imperas-riscv-tests/work/",
"/home/harris/github/riscv-arch-test/work/" "../../addins/riscv-arch-test/work/"
}; };
string imperas32mmu[] = '{ string imperas32mmu[] = '{