From 00d80358364a3caa8e8f265dd6f3ec232c7d163f Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 18 Oct 2021 15:43:59 -0700
Subject: [PATCH] Fixed multiplier and pointed arch tests to new path in addins

---
 wally-pipelined/src/muldiv/mul.sv          | 6 ------
 wally-pipelined/src/muldiv/redundantmul.sv | 8 ++++++--
 wally-pipelined/testbench/tests.vh         | 2 +-
 3 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/wally-pipelined/src/muldiv/mul.sv b/wally-pipelined/src/muldiv/mul.sv
index cff07e67..5ab8b73a 100644
--- a/wally-pipelined/src/muldiv/mul.sv
+++ b/wally-pipelined/src/muldiv/mul.sv
@@ -60,10 +60,6 @@ module mul (
   // Execute Stage: Compute partial products
   //////////////////////////////
 
-    // portions of product
-    //assign Pprime = {1'b0, SrcAE[`XLEN-2:0]} * {1'b0, SrcBE[`XLEN-2:0]};
-
-    // *** assumes unsigned multiplication
     assign Aprime = {1'b0, SrcAE[`XLEN-2:0]};
     assign Bprime = {1'b0, SrcBE[`XLEN-2:0]};
     redundantmul #(`XLEN) bigmul(.a(Aprime), .b(Bprime), .out0(PP0E), .out1(PP1E));
@@ -77,8 +73,6 @@ module mul (
     // assign MULHU = (Funct3E == 2'b11); // signal unused
 
     // Handle signs
-//    assign PP0E = 0;
-//    assign PP1E = Pprime; // same for all flavors
     assign PP2E = {2'b00, (MULH | MULHSU) ? ~PA : PA, {(`XLEN-1){1'b0}}};
     assign PP3E = {2'b00, (MULH) ? ~PB : PB, {(`XLEN-1){1'b0}}};
     always_comb 
diff --git a/wally-pipelined/src/muldiv/redundantmul.sv b/wally-pipelined/src/muldiv/redundantmul.sv
index 23e85a26..1f94db62 100644
--- a/wally-pipelined/src/muldiv/redundantmul.sv
+++ b/wally-pipelined/src/muldiv/redundantmul.sv
@@ -31,9 +31,13 @@ module redundantmul #(parameter WIDTH =8)(
 
   generate
      if (`DESIGN_COMPILER == 1)
-       DW02_multp #(WIDTH, WIDTH, 2*WIDTH) bigmul(.a, .b, .tc(1'b0), .out0, .out1);
+       DW02_multp #(WIDTH, WIDTH, 2*WIDTH) mul(.a, .b, .tc(1'b0), .out0, .out1);
      else if (`DESIGN_COMPILER == 2)
-       mult_cs #(WIDTH) hackymul (.a, .b, .tc(1'b0), .sum(out0), .carry(out1));
+       mult_cs #(WIDTH) mul(.a, .b, .tc(1'b0), .sum(out0), .carry(out1));
+     else begin // force a nonredunant multipler.  This will simulate properly and also is appropriate for FPGAs.
+       assign out0 = a * b;
+       assign out1 = 0;
+     end
   endgenerate
 
 endmodule
diff --git a/wally-pipelined/testbench/tests.vh b/wally-pipelined/testbench/tests.vh
index 7b5b5ea6..c96b165d 100644
--- a/wally-pipelined/testbench/tests.vh
+++ b/wally-pipelined/testbench/tests.vh
@@ -28,7 +28,7 @@
 
 string tvpaths[] = '{
     "../../imperas-riscv-tests/work/",
-    "/home/harris/github/riscv-arch-test/work/"
+    "../../addins/riscv-arch-test/work/"
 };
 
   string imperas32mmu[] = '{