This website requires JavaScript.
Explore
Help
Register
Sign In
Xavi
/
cvw
Watch
1
Star
0
Fork
0
You've already forked cvw
forked from
Github_Repos/cvw
Code
Issues
Pull Requests
Packages
Projects
Releases
Wiki
Activity
cb54e95285
cvw
/
pipelined
/
regression
/
sim-wally
3 lines
55 B
Plaintext
Raw
Normal View
History
Unescape
Escape
Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.
2022-08-28 03:31:09 +00:00
vsim -do "do wally-pipelined.do rv32ic wally32periph"
Major reorganization of regression and simulation and testbenches
2021-10-10 22:07:51 +00:00
Reference in New Issue
Copy Permalink
Home