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///////////////////////////////////////////
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// pmachecker.sv
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//
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// Written: tfleming@hmc.edu & jtorrey@hmc.edu 20 April 2021
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// Modified:
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//
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// Purpose: Examines all physical memory accesses and identifies attributes of
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// the memory region accessed.
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// Can report illegal accesses to the trap unit and cause a fault.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module pmachecker (
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input logic clk, reset,
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input logic [31:0] HADDR,
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input logic [2:0] HSIZE,
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input logic [2:0] HBURST,
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input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,
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output logic Cacheable, Idempotent, AtomicAllowed,
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output logic PMASquashBusAccess,
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output logic [5:0] HSELRegions,
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output logic PMAInstrAccessFaultF,
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output logic PMALoadAccessFaultM,
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output logic PMAStoreAccessFaultM
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);
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// Signals are high if the memory access is within the given region
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logic HSELBootTim, HSELTim, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC;
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logic PreHSELUART;
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logic ExecutableRegion, ReadableRegion, WritableRegion;
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logic Empty;
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// Determine which region of physical memory (if any) is being accessed
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adrdec boottimdec(HADDR, `BOOTTIMBASE, `BOOTTIMRANGE, HSELBootTim);
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adrdec timdec(HADDR, `TIMBASE, `TIMRANGE, HSELTim);
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adrdec clintdec(HADDR, `CLINTBASE, `CLINTRANGE, HSELCLINT);
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adrdec gpiodec(HADDR, `GPIOBASE, `GPIORANGE, HSELGPIO);
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adrdec uartdec(HADDR, `UARTBASE, `UARTRANGE, PreHSELUART);
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adrdec plicdec(HADDR, `PLICBASE, `PLICRANGE, HSELPLIC);
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// *** Should this fault?
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assign HSELUART = PreHSELUART && (HSIZE == 3'b000); // only byte writes to UART are supported
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// Swizzle region bits
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assign HSELRegions = {HSELBootTim, HSELTim, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC};
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// Only RAM memory regions are cacheable
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assign Cacheable = HSELBootTim | HSELTim;
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// *** Temporarily assume only RAM regions are idempotent -- likely wrong
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assign Idempotent = HSELBootTim | HSELTim;
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// *** Temporarily assume only RAM regions allow full atomic operations -- likely wrong
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assign AtomicAllowed = HSELBootTim | HSELTim;
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assign ExecutableRegion = HSELBootTim | HSELTim;
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assign ReadableRegion = HSELBootTim | HSELTim | HSELCLINT | HSELGPIO | HSELUART | HSELPLIC;
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assign WritableRegion = HSELBootTim | HSELTim | HSELCLINT | HSELGPIO | HSELUART | HSELPLIC;
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assign Empty = ~|HSELRegions;
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assign PMAInstrAccessFaultF = ExecuteAccessF && (Empty || ~ExecutableRegion);
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assign PMALoadAccessFaultM = ReadAccessM && (Empty || ~ReadableRegion);
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assign PMAStoreAccessFaultM = WriteAccessM && (Empty || ~WritableRegion);
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//assign PMASquashBusAccess = PMAInstrAccessFaultF || PMALoadAccessFaultM || PMAStoreAccessFaultM;
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assign PMASquashBusAccess = 0;
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2021-04-26 16:48:58 +00:00
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endmodule
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