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///////////////////////////////////////////
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// pmpchecker.sv
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//
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2021-04-29 06:20:39 +00:00
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// Written: tfleming@hmc.edu & jtorrey@hmc.edu 28 April 2021
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// Modified:
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//
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// Purpose: Examines all physical memory accesses and checks them against the
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// current values of the physical memory protection (PMP) registers.
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// Can raise an access fault on illegal reads, writes, and instruction
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// fetches.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module pmpchecker (
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input logic clk, reset,
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input logic [31:0] HADDR,
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input logic [1:0] PrivilegeModeW,
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input logic [1:0] STATUS_MPP,
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input logic STATUS_MPRV,
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input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW,
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input logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15],
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input logic ExecuteAccessF, WriteAccessM, ReadAccessM,
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output logic PMPSquashBusAccess,
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output logic PMPInstrAccessFaultF,
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output logic PMPLoadAccessFaultM,
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output logic PMPStoreAccessFaultM
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);
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// Bit i is high when the address falls in PMP region i
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logic [15:0] Regions;
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logic [3:0] MatchedRegion;
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logic Match, EnforcePMP;
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logic [7:0] PMPCFG [0:15];
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// Bit i is high when the address is greater than or equal to PMPADR[i]
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// Used for determining whether TOR PMP regions match
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logic [15:0] AboveRegion;
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// Bit i is high if PMP register i is non-null
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logic [15:0] ActiveRegion;
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logic L_Bit, X_Bit, W_Bit, R_Bit;
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logic InvalidExecute, InvalidWrite, InvalidRead;
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assign {PMPCFG[15], PMPCFG[14], PMPCFG[13], PMPCFG[12],
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PMPCFG[11], PMPCFG[10], PMPCFG[9], PMPCFG[8]} = PMPCFG23_REGW;
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assign {PMPCFG[7], PMPCFG[6], PMPCFG[5], PMPCFG[4],
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PMPCFG[3], PMPCFG[2], PMPCFG[1], PMPCFG[0]} = PMPCFG01_REGW;
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pmpadrdec pmpadrdec(.HADDR(HADDR), .AdrMode(PMPCFG[0][4:3]),
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.CurrentPMPAdr(PMPADDR_ARRAY_REGW[0]),
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.AdrAtLeastPreviousPMP(1'b1),
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.AdrAtLeastCurrentPMP(AboveRegion[0]),
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.Match(Regions[0]));
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assign ActiveRegion[0] = |PMPCFG[0][4:3];
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generate
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genvar i;
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for (i = 1; i < 16; i++) begin
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pmpadrdec pmpadrdec(.HADDR(HADDR), .AdrMode(PMPCFG[i][4:3]),
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.CurrentPMPAdr(PMPADDR_ARRAY_REGW[i]),
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.AdrAtLeastPreviousPMP(AboveRegion[i-1]),
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.AdrAtLeastCurrentPMP(AboveRegion[i]),
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.Match(Regions[i]));
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assign ActiveRegion[i] = |PMPCFG[i][4:3];
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end
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endgenerate
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assign Match = |Regions;
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// Only enforce PMP checking for S and U modes when at least one PMP is active
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assign EnforcePMP = |ActiveRegion;
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always_comb
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casez (Regions)
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16'b???????????????1: MatchedRegion = 0;
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16'b??????????????10: MatchedRegion = 1;
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16'b?????????????100: MatchedRegion = 2;
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16'b????????????1000: MatchedRegion = 3;
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16'b???????????10000: MatchedRegion = 4;
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16'b??????????100000: MatchedRegion = 5;
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16'b?????????1000000: MatchedRegion = 6;
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16'b????????10000000: MatchedRegion = 7;
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16'b???????100000000: MatchedRegion = 8;
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16'b??????1000000000: MatchedRegion = 9;
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16'b?????10000000000: MatchedRegion = 10;
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16'b????100000000000: MatchedRegion = 11;
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16'b???1000000000000: MatchedRegion = 12;
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16'b??10000000000000: MatchedRegion = 13;
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16'b?100000000000000: MatchedRegion = 14;
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16'b1000000000000000: MatchedRegion = 15;
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default: MatchedRegion = 0; // Should only occur if there is no match
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endcase
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assign L_Bit = PMPCFG[MatchedRegion][7] && Match;
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assign X_Bit = PMPCFG[MatchedRegion][2] && Match;
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assign W_Bit = PMPCFG[MatchedRegion][1] && Match;
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assign R_Bit = PMPCFG[MatchedRegion][0] && Match;
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assign InvalidExecute = ExecuteAccessF && ~X_Bit;
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assign InvalidWrite = WriteAccessM && ~W_Bit;
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assign InvalidRead = ReadAccessM && ~R_Bit;
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assign PMPInstrAccessFaultF = (PrivilegeModeW == `M_MODE) ?
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Match && L_Bit && InvalidExecute :
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EnforcePMP && InvalidExecute;
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assign PMPStoreAccessFaultM = (PrivilegeModeW == `M_MODE) ?
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Match && L_Bit && InvalidWrite :
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EnforcePMP && InvalidWrite;
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assign PMPLoadAccessFaultM = (PrivilegeModeW == `M_MODE) ?
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Match && L_Bit && InvalidRead :
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EnforcePMP && InvalidRead;
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/*
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assign PMPInstrAccessFaultF = 1'b0;
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assign PMPStoreAccessFaultM = 1'b0;
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assign PMPLoadAccessFaultM = 1'b0;
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*/
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/*
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If no PMP entry matches an M-mode access, the access succeeds. If no PMP entry matches an
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S-mode or U-mode access, but at least one PMP entry is implemented, the access fails.
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*/
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assign PMPSquashBusAccess = PMPInstrAccessFaultF || PMPLoadAccessFaultM || PMPStoreAccessFaultM;
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endmodule
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