cvw/.gitignore

**/work*
**/wally_*.log

.nfs*

__pycache__/
.vscode/

#External repos
addins
addins/riscv-arch-test/Makefile.include
addins/riscv-tests/target

#vsim work files to ignore
transcript
vsim.wlf
pipelined/wlft*
wlft*
/imperas-riscv-tests/FunctionRadix_32.addr
/imperas-riscv-tests/FunctionRadix_64.addr
/imperas-riscv-tests/FunctionRadix.addr
/imperas-riscv-tests/ProgramMap.txt
/imperas-riscv-tests/logs
*.o
*.d
*.vstf
testsBP/*/*/*.elf*
testsBP/*/OBJ/*
testsBP/*/*.a
tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/*
tests/linux-testgen/linux-testvectors/*
!tests/linux-testgen/linux-testvectors/tvCopier.py
!tests/linux-testgen/linux-testvectors/tvLinker.sh
!tests/linux-testgen/linux-testvectors/tvUnlinker.sh
tests/linux-testgen/buildroot
tests/linux-testgen/buildroot-image-output
tests/linux-testgen/buildroot-config-src/main.config.old
tests/linux-testgen/buildroot-config-src/linux.config.old
tests/linux-testgen/buildroot-config-src/busybox.config.old
pipelined/regression/slack-notifier/slack-webhook-url.txt
pipelined/regression/logs
fpga/generator/IP
fpga/generator/vivado.*
fpga/generator/.Xil/*
fpga/generator/WallyFPGA*
fpga/generator/reports/
fpga/generator/*.log
fpga/generator/*.jou
*.objdump*
*.signature.output
examples/asm/sumtest/sumtest
examples/asm/example/example
examples/C/sum/sum
examples/C/fir/fir
examples/fp/softfloat_demo/softfloat_demo
examples/fp/fpcalc/fpcalc
pipelined/src/fma/fma16_testgen
linux/devicetree/debug/*
!linux/devicetree/debug/dump-dts.sh
linux/testvector-generation/genCheckpoint.gdb
linux/testvector-generation/silencePipe
linux/testvector-generation/silencePipe.control
linux/testvector-generation/fixBinMem
linux/testvector-generation/qemu-serial
*.dtb
synthDC/WORK
synthDC/alib-52
synthDC/*.log
synthDC/*.svf
synthDC/runs/
synthDC/hdl
/pipelined/regression/power.saif
tests/fp/vectors/*.tv
Add the regression logs and new regression byproducts to the gitignore 2021-02-02 15:43:41 +00:00			`*/work`
			`*/wally_.log`
More testbench setup work - Copy bare-bones testbench from E85 - have testbench instantiate a wallypipelinedhart so we can simulate memory/peripherals easier - Create .gitignore for vsim files - Make PC reset a macro, change to 0x1000 to conform to the bootloader I don't know a good way to put the linux register trace file we're generating on git, since its both nontrivial to make and way to big to keep in a git repo for now it lives in /mnt/scratch/riscv_testbench/ 2021-01-21 22:55:05 +00:00
add .nfs* files to gitignore 2021-02-28 20:48:01 +00:00			`.nfs*`

Add vscode and pycache folders to .gitignore 2021-03-25 06:37:50 +00:00			`__pycache__/`
			`.vscode/`

gitignore the addins folder because it contains external repos 2021-10-19 20:32:26 +00:00			`#External repos`
			`addins`
Fixed .gitignore 2021-12-29 18:58:36 +00:00			`addins/riscv-arch-test/Makefile.include`
lsu cleanup down to 346 lines 2022-01-15 01:19:44 +00:00			`addins/riscv-tests/target`
gitignore the addins folder because it contains external repos 2021-10-19 20:32:26 +00:00
More testbench setup work - Copy bare-bones testbench from E85 - have testbench instantiate a wallypipelinedhart so we can simulate memory/peripherals easier - Create .gitignore for vsim files - Make PC reset a macro, change to 0x1000 to conform to the bootloader I don't know a good way to put the linux register trace file we're generating on git, since its both nontrivial to make and way to big to keep in a git repo for now it lives in /mnt/scratch/riscv_testbench/ 2021-01-21 22:55:05 +00:00			`#vsim work files to ignore`
			`transcript`
			`vsim.wlf`
Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00			`pipelined/wlft*`
Busybear test now processes first 100 instrs correctly! - changed test parser to recognize lw in addition to lw also, added temporary questa files (wlft*) to .gitignore 2021-01-28 06:16:39 +00:00			`wlft*`
Added debug option to disable the function radix if not needed. Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests. 2021-03-10 21:17:02 +00:00			`/imperas-riscv-tests/FunctionRadix_32.addr`
			`/imperas-riscv-tests/FunctionRadix_64.addr`
gitignore FunctionRadix.addr 2021-03-25 04:13:46 +00:00			`/imperas-riscv-tests/FunctionRadix.addr`
Added debug option to disable the function radix if not needed. Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests. 2021-03-10 21:17:02 +00:00			`/imperas-riscv-tests/ProgramMap.txt`
script for running make and logging output 2021-05-18 02:12:18 +00:00			`/imperas-riscv-tests/logs`
Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally. 2021-03-31 04:18:20 +00:00			`*.o`
			`*.d`
Added files to repo 2021-12-05 04:25:33 +00:00			`*.vstf`
Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally. 2021-03-31 04:18:20 +00:00			`testsBP///.elf`
			`testsBP//OBJ/`
			`testsBP//.a`
Updated configs to fix GPIO address to match FU540 2022-01-26 18:16:34 +00:00			`tests/wally-riscv-arch-test/riscv-test-suite//I//*`
linux testgen refactor 2021-11-01 21:09:49 +00:00			`tests/linux-testgen/linux-testvectors/*`
			`!tests/linux-testgen/linux-testvectors/tvCopier.py`
			`!tests/linux-testgen/linux-testvectors/tvLinker.sh`
			`!tests/linux-testgen/linux-testvectors/tvUnlinker.sh`
			`tests/linux-testgen/buildroot`
			`tests/linux-testgen/buildroot-image-output`
			`tests/linux-testgen/buildroot-config-src/main.config.old`
			`tests/linux-testgen/buildroot-config-src/linux.config.old`
			`tests/linux-testgen/buildroot-config-src/busybox.config.old`
Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00			`pipelined/regression/slack-notifier/slack-webhook-url.txt`
			`pipelined/regression/logs`
Created Makefile to manage IP generation. 2021-11-30 00:32:51 +00:00			`fpga/generator/IP`
Added make clean to fpga IP generator. 2021-11-30 00:42:28 +00:00			`fpga/generator/vivado.*`
Updated .gitignore file to hide fpga outputs. 2021-12-14 00:30:10 +00:00			`fpga/generator/.Xil/*`
			`fpga/generator/WallyFPGA*`
			`fpga/generator/reports/`
			`fpga/generator/*.log`
			`fpga/generator/*.jou`
Fixed .gitignore 2021-12-29 18:58:36 +00:00			`.objdump`
			`*.signature.output`
			`examples/asm/sumtest/sumtest`
lsu cleanup down to 346 lines 2022-01-15 01:19:44 +00:00			`examples/asm/example/example`
Updated configs to fix GPIO address to match FU540 2022-01-26 18:16:34 +00:00			`examples/C/sum/sum`
Replaced \|\| and && with \| and & 2022-01-31 01:07:35 +00:00			`examples/C/fir/fir`
Created softfloat_demo showcasing how to do math with SoftFloat 2022-02-27 18:17:21 +00:00			`examples/fp/softfloat_demo/softfloat_demo`
Enhanced printing intermediate results in fpcalc.c 2022-02-28 04:15:20 +00:00			`examples/fp/fpcalc/fpcalc`
Created softfloat_demo showcasing how to do math with SoftFloat 2022-02-27 18:17:21 +00:00			`pipelined/src/fma/fma16_testgen`
add trimmed-down virt devicetree to repo for QEMU 2022-02-08 11:11:44 +00:00			`linux/devicetree/debug/*`
rename dump-dts debug script 2022-02-10 00:10:09 +00:00			`!linux/devicetree/debug/dump-dts.sh`
revived checkpointing and hacked it up to generate a trace starting at the checkpoint 2022-02-25 23:51:40 +00:00			`linux/testvector-generation/genCheckpoint.gdb`
			`linux/testvector-generation/silencePipe`
			`linux/testvector-generation/silencePipe.control`
			`linux/testvector-generation/fixBinMem`
greatly improve trace-generating checkpoint process with QEMU hack 2022-02-28 23:00:00 +00:00			`linux/testvector-generation/qemu-serial`
gitignore dtb's because we only care about dts's as being source files 2022-02-08 11:14:59 +00:00			`*.dtb`
Cleaned up synthesis flow. 2022-02-09 21:18:49 +00:00			`synthDC/WORK`
			`synthDC/alib-52`
			`synthDC/*.log`
			`synthDC/*.svf`
			`synthDC/runs/`
			`synthDC/hdl`
Ignore saif files. 2022-02-10 01:30:26 +00:00			`/pipelined/regression/power.saif`
Added bootmem source ccode 2022-04-05 23:22:53 +00:00			`tests/fp/vectors/*.tv`