cvw/README.md

# riscv-wally
Configurable RISC-V Processor

Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, and M extensions, FENCE.I, and the various privileged modes and CSRs.  It is written in SystemVerilog.  It passes the RISC-V Arch Tests and Imperas tests.  As of October 2021, it boots the first 10 million instructions of Buildroot Linux.

See Chapter 2 of draft book of how to install and compile tests.
Initial commit 2021-01-15 04:16:47 +00:00			`# riscv-wally`
			`Configurable RISC-V Processor`
Update README.md 2021-10-11 15:13:15 +00:00
			`Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, and M extensions, FENCE.I, and the various privileged modes and CSRs. It is written in SystemVerilog. It passes the RISC-V Arch Tests and Imperas tests. As of October 2021, it boots the first 10 million instructions of Buildroot Linux.`

Update README.md 2022-01-05 19:29:54 +00:00			`See Chapter 2 of draft book of how to install and compile tests.`