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Configurable RISC-V Processor
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David Harris 2dc73574d3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-24 23:21:16 +00:00
addins Fixed sumtest reference output; added embench benchmark directory 2022-01-24 23:21:09 +00:00
benchmarks Fixed sumtest reference output; added embench benchmark directory 2022-01-24 23:21:09 +00:00
bin Added E extension, and downloaded riscv-dv and embench-iot to addins 2022-01-17 14:42:59 +00:00
examples Fixed sumtest reference output; added embench benchmark directory 2022-01-24 23:21:09 +00:00
fpga Renamed wallypipelinedhart to wallypipelinedcore 2022-01-20 16:02:08 +00:00
linux Created linux directory for linux config 2022-01-20 00:04:23 +00:00
pipelined Added spill support back into the IROM IFU. 2022-01-21 15:50:54 -06:00
tests added qemu patches in tests/linux-testgen/qemu 2022-01-24 07:52:07 +00:00
.gitattributes Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
.gitignore lsu cleanup down to 346 lines 2022-01-15 01:19:44 +00:00
.gitmodules Added E extension, and downloaded riscv-dv and embench-iot to addins 2022-01-17 14:42:59 +00:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
Makefile Fixed path to riscvOVPsimPlus 2022-01-21 00:12:14 +00:00
README.md Update README.md 2022-01-05 11:29:54 -08:00
setup.sh Fixed sumtest reference output; added embench benchmark directory 2022-01-24 23:21:09 +00:00

README.md

riscv-wally

Configurable RISC-V Processor

Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, and M extensions, FENCE.I, and the various privileged modes and CSRs. It is written in SystemVerilog. It passes the RISC-V Arch Tests and Imperas tests. As of October 2021, it boots the first 10 million instructions of Buildroot Linux.

See Chapter 2 of draft book of how to install and compile tests.