cvw/pipelined/regression/lint-wally

#!/bin/bash
# check for warnings in Verilog code
# The verilator lint tool is faster and better than Modelsim so it is best to run this first.
export PATH=$PATH:/usr/local/bin/
verilator=`which verilator`

basepath=$(dirname $0)/..
#for config in rv32e rv64gc rv32gc rv32ic rv32i rv64i rv64fpquad; do
for config in  rv64gc; do
    echo "$config linting..."
    if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
        echo "Exiting after $config lint due to errors or warnings"
        exit 1
    fi
done
echo "All lints run with no errors or warnings"

# --lint-only just runs lint rather than trying to compile and simulate
# -I points to the include directory where files such as `include wally-config.vh  are found

# For more exhaustive (and sometimes spurious) warnings, add --Wall to the Verilator command
# Unfortunately, this produces a bunch of UNUSED and UNDRIVEN signal warnings in blocks that are configured to not exist.