2022-01-31 16:28:12 +00:00
|
|
|
///////////////////////////////////////////
|
|
|
|
// atomic.sv
|
|
|
|
//
|
|
|
|
// Written: Ross Thompson ross1728@gmail.com January 31, 2022
|
|
|
|
// Modified:
|
|
|
|
//
|
|
|
|
// Purpose: atomic data path.
|
|
|
|
//
|
2023-01-11 23:15:08 +00:00
|
|
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
2022-01-31 16:28:12 +00:00
|
|
|
//
|
2023-01-10 19:35:20 +00:00
|
|
|
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
2022-01-31 16:28:12 +00:00
|
|
|
//
|
2023-01-10 19:35:20 +00:00
|
|
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
2022-01-31 16:28:12 +00:00
|
|
|
//
|
2023-01-10 19:35:20 +00:00
|
|
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
|
|
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
|
|
|
// may obtain a copy of the License at
|
2022-01-31 16:28:12 +00:00
|
|
|
//
|
2023-01-10 19:35:20 +00:00
|
|
|
// https://solderpad.org/licenses/SHL-2.1/
|
|
|
|
//
|
|
|
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
|
|
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
|
|
|
// either express or implied. See the License for the specific language governing permissions
|
|
|
|
// and limitations under the License.
|
2022-01-31 16:28:12 +00:00
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
|
|
|
`include "wally-config.vh"
|
|
|
|
|
|
|
|
module atomic (
|
|
|
|
input logic clk,
|
2022-05-12 14:49:58 +00:00
|
|
|
input logic reset, StallW,
|
2022-01-31 16:28:12 +00:00
|
|
|
input logic [`XLEN-1:0] ReadDataM,
|
2022-11-13 18:27:48 +00:00
|
|
|
input logic [`XLEN-1:0] IHWriteDataM,
|
2022-09-13 16:47:39 +00:00
|
|
|
input logic [`PA_BITS-1:0] PAdrM,
|
2022-01-31 16:28:12 +00:00
|
|
|
input logic [6:0] LSUFunct7M,
|
|
|
|
input logic [2:0] LSUFunct3M,
|
|
|
|
input logic [1:0] LSUAtomicM,
|
|
|
|
input logic [1:0] PreLSURWM,
|
|
|
|
input logic IgnoreRequest,
|
2022-08-23 15:34:39 +00:00
|
|
|
output logic [`XLEN-1:0] IMAWriteDataM,
|
2022-01-31 16:28:12 +00:00
|
|
|
output logic SquashSCW,
|
2023-01-16 02:23:09 +00:00
|
|
|
output logic [1:0] LSURWM
|
|
|
|
);
|
2022-01-31 16:28:12 +00:00
|
|
|
|
2023-01-16 02:23:09 +00:00
|
|
|
logic [`XLEN-1:0] AMOResult;
|
|
|
|
logic MemReadM;
|
2022-01-31 16:28:12 +00:00
|
|
|
|
2022-11-13 18:27:48 +00:00
|
|
|
amoalu amoalu(.srca(ReadDataM), .srcb(IHWriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]),
|
2022-03-04 00:07:31 +00:00
|
|
|
.result(AMOResult));
|
2023-01-16 02:23:09 +00:00
|
|
|
|
2022-11-13 18:27:48 +00:00
|
|
|
mux2 #(`XLEN) wdmux(IHWriteDataM, AMOResult, LSUAtomicM[1], IMAWriteDataM);
|
2022-03-11 00:56:37 +00:00
|
|
|
assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
|
2023-01-16 02:23:09 +00:00
|
|
|
|
|
|
|
lrsc lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM);
|
2022-01-31 16:28:12 +00:00
|
|
|
|
|
|
|
endmodule
|