David Harris d3ce683e06 Removed other unused signals from Verilog		2023-11-20 23:37:56 -08:00
..
align.sv	Fixed Zicclsm bug. Misalignment and spill detection were not masked by access type. Therefore a page table walk which always aligned could have had an IEUAdrM misaligned which erroneously caused a shift in the read data.	2023-11-18 19:01:39 -06:00
amoalu.sv
atomic.sv
dtim.sv	Modified rams to take USE_SRAM rather than P to facilitate synthesis	2023-11-03 05:44:13 -07:00
endianswap.sv
lrsc.sv	Update lrsc.sv	2023-06-12 13:14:36 -07:00
lsu.sv	Removed other unused signals from Verilog	2023-11-20 23:37:56 -08:00
subwordread.sv	Progress on misaligned load/stores.	2023-10-27 09:35:44 -05:00
subwordwrite.sv	Update subwordwrite.sv	2023-06-12 13:35:27 -07:00
swbytemask.sv	Merge branch 'main' into Zicclsm	2023-11-02 12:55:51 -05:00