David Harris 98176665de Fixed messed-up hazard.sv		2023-11-15 08:05:41 -08:00
..
cache	Merge branch 'main' into Zicclsm	2023-11-10 16:15:32 -06:00
ebu	Merge branch 'main' into Zicclsm	2023-11-02 12:55:51 -05:00
fpu	Removed assign statement inside always block	2023-11-13 07:23:15 -08:00
generic	set default USE_SRAM=0 in memories; cleaned up synthesis script grep for cvw_t	2023-11-03 06:37:05 -07:00
hazard	Fixed messed-up hazard.sv	2023-11-15 08:05:41 -08:00
ieu	minfo test working again with mconfigptr for RV64	2023-10-15 06:41:52 -07:00
ifu	Modified rams to take USE_SRAM rather than P to facilitate synthesis	2023-11-03 05:44:13 -07:00
lsu	Fixed bug in uncore updates which broke SDC.	2023-11-13 16:15:23 -06:00
mdu	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-06-15 15:38:38 -05:00
mmu	Merge branch 'main' into Zicclsm	2023-11-10 16:15:32 -06:00
privileged	Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.	2023-10-30 09:56:17 -07:00
uncore	Merge branch 'spi' into main	2023-11-14 14:51:06 -08:00
wally	Removed unused addins, cleaned up configuration to support half precision on RV64gc, gate unused hazard inputs to reduce critical path in rv32e	2023-11-14 11:01:58 -08:00
cvw.sv	Merge pull request #472 from ross144/main	2023-11-14 08:34:06 -08:00