mirror of
https://github.com/openhwgroup/cvw
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111 lines
4.3 KiB
Systemverilog
111 lines
4.3 KiB
Systemverilog
///////////////////////////////////////////
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// ram_ahb.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: On-chip RAM, external to core, with AHB interface
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//
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// Documentation: RISC-V System on Chip Design
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module ram_ahb import cvw::*; #(parameter cvw_t P,
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parameter RANGE = 65535, PRELOAD = 0) (
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input logic HCLK, HRESETn,
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input logic HSELRam,
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input logic [P.PA_BITS-1:0] HADDR,
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input logic HWRITE,
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input logic HREADY,
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input logic [1:0] HTRANS,
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input logic [P.XLEN-1:0] HWDATA,
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input logic [P.XLEN/8-1:0] HWSTRB,
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output logic [P.XLEN-1:0] HREADRam,
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output logic HRESPRam, HREADYRam
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);
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localparam ADDR_WIDTH = $clog2(RANGE/8);
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localparam OFFSET = $clog2(P.XLEN/8);
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logic [P.XLEN/8-1:0] ByteMask;
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logic [P.PA_BITS-1:0] HADDRD, RamAddr;
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logic initTrans;
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logic memwrite, memwriteD, memread;
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logic nextHREADYRam;
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logic DelayReady;
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// a new AHB transactions starts when HTRANS requests a transaction,
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// the peripheral is selected, and the previous transaction is completing
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assign initTrans = HREADY & HSELRam & HTRANS[1] ;
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assign memwrite = initTrans & HWRITE;
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assign memread = initTrans & ~HWRITE;
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flopenr #(1) memwritereg(HCLK, ~HRESETn, HREADY, memwrite, memwriteD);
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flopenr #(P.PA_BITS) haddrreg(HCLK, ~HRESETn, HREADY, HADDR, HADDRD);
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// Stall on a read after a write because the RAM can't take both adddresses on the same cycle
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assign nextHREADYRam = (~(memwriteD & memread)) & ~DelayReady;
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flopr #(1) readyreg(HCLK, ~HRESETn, nextHREADYRam, HREADYRam);
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assign HRESPRam = 1'b0; // OK
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// On writes or during a wait state, use address delayed by one cycle to sync RamAddr with HWDATA or hold stalled address
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mux2 #(P.PA_BITS) adrmux(HADDR, HADDRD, memwriteD | ~HREADY, RamAddr);
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// single-ported RAM
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ram1p1rwbe #(P.USE_SRAM, RANGE/8, P.XLEN, PRELOAD) memory(.clk(HCLK), .ce(1'b1),
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.addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HREADRam));
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// use this to add arbitrary latency to ram. Helps test AHB controller correctness
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if(P.RAM_LATENCY > 0) begin
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logic [7:0] NextCycle, Cycle;
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logic CntEn, CntRst;
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logic CycleFlag;
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flopenr #(8) counter (HCLK, ~HRESETn | CntRst, CntEn, NextCycle, Cycle);
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assign NextCycle = Cycle + 1'b1;
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typedef enum logic {READY, DELAY} statetype;
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statetype CurrState, NextState;
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always_ff @(posedge HCLK)
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if (~HRESETn) CurrState <= READY;
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else CurrState <= NextState;
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always_comb begin
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case(CurrState)
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READY: if(initTrans & ~CycleFlag) NextState = DELAY;
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else NextState = READY;
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DELAY: if(CycleFlag) NextState = READY;
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else NextState = DELAY;
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default: NextState = READY;
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endcase
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end
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assign CycleFlag = Cycle == P.RAM_LATENCY[7:0];
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assign CntEn = NextState == DELAY;
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assign DelayReady = NextState == DELAY;
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assign CntRst = NextState == READY;
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end else begin
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assign DelayReady = 1'b0;
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end
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endmodule
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