Rose Thompson 626b89320c More cleanup.		2023-12-29 16:51:39 -06:00
..
cache	Cleanup.	2023-12-29 16:18:30 -06:00
ebu	Added partial code for uncached amo operations.	2023-12-29 15:07:20 -06:00
fpu	Removed other unused signals from Verilog	2023-11-20 23:37:56 -08:00
generic	Revert RAM logic to bit change.	2023-12-20 13:10:20 -06:00
hazard	Moved forwarding logic into controller	2023-12-26 21:17:01 -08:00
ieu	More cleanup.	2023-12-29 16:51:39 -06:00
ifu	Restored cache store delay hazard.	2023-12-29 16:10:27 -06:00
lsu	Cleanup.	2023-12-29 16:18:30 -06:00
mdu	turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep	2023-11-17 20:25:24 -08:00
mmu	Renamed CMOp to CMOpM in mmu and cache	2023-12-25 05:57:41 -08:00
privileged	Moved forwarding logic into controller	2023-12-26 21:17:01 -08:00
uncore	Reversed numbering of adrdecs to make it easier to add new peripherals without renumbering the old ones; update figure to match	2023-12-21 12:29:37 -08:00
wally	Moved forwarding logic into controller	2023-12-26 21:17:01 -08:00
cvw.sv	Added parameter for cache's SRAM length.	2023-12-18 12:50:49 -06:00