cvw/fpga/generator
Ross Thompson b756b248b4 Wow. The newest version of Vivado does not like the enums as parameters.
The solution is simple.  I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
2023-07-18 15:07:10 -05:00
..
debug
bootrom.txt
insert_debug_comment.sh
Makefile Wow. The newest version of Vivado does not like the enums as parameters. 2023-07-18 15:07:10 -05:00
probe
wally.tcl FPGA updates. 2023-06-20 11:11:34 -05:00
wave_config.wcfg Updated fpga wave config. 2023-06-19 12:28:30 -05:00
xlnx_ahblite_axi_bridge.tcl Added more support for Arty A7 board. 2023-04-10 16:01:17 -05:00
xlnx_axi_clock_converter.tcl Added more support for Arty A7 board. 2023-04-10 16:01:17 -05:00
xlnx_ddr3-artya7-mig.prj It's almost working. 2023-04-18 14:24:59 -05:00
xlnx_ddr3-ArtyA7.tcl Finally fixed the ddr3 mig script to work correclty. 2023-04-14 11:41:51 -05:00
xlnx_ddr4-vcu108.tcl
xlnx_ddr4-vcu118.tcl
xlnx_ddr4.tcl
xlnx_mmcm.tcl Lowered arty a7 clock frequency to 15Mhz to meet timing. can probalby go faster. 2023-04-17 12:16:31 -05:00
xlnx_proc_sys_reset.tcl Added more support for Arty A7 board. 2023-04-10 16:01:17 -05:00