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slack-notifier
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added instructions to slack notifier
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2022-05-18 16:50:31 -07:00 |
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wave-dos
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Added generate around uncore.
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2022-08-25 10:35:24 -05:00 |
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wkdir
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added wkdir in regression so regression runs out of box (assuming the old version of arch tests)
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2022-05-17 20:32:38 +00:00 |
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buildrootBugFinder.py
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update to match new filesystem organization
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2022-03-26 21:28:32 +00:00 |
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fpga-wave.do
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Merged together bram1p1rw with sram1p1rw as sram1p1rw.
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2022-09-21 12:20:00 -05:00 |
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lint-wally
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Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width
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2022-10-10 09:10:55 -07:00 |
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linux-wave.do
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Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks.
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2022-10-23 13:46:50 -05:00 |
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make-tests.sh
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simplified make-tests.sh to run the current makefile in regression
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2022-05-17 17:29:34 -07:00 |
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Makefile
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More riscof makefile tuning
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2022-07-25 21:15:56 +00:00 |
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makefile-memfile
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plic-s debug
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2022-08-03 12:33:09 +00:00 |
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regression-wally
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Removed imperas tests from rv32i/rv64i because the configs lack privileged support expected in the tests. Also cleaned up comment in LSU
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2022-10-10 10:22:12 -07:00 |
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sim-buildroot
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switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv
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2022-03-01 03:11:43 +00:00 |
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sim-buildroot-batch
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sim-buildroot-batch now runs wally-pipelined-batch
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2022-07-06 18:06:43 -07:00 |
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sim-testfloat
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Running 16-bit square root cases first in testfloat
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2022-09-07 11:11:35 -07:00 |
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sim-testfloat-batch
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fixed error in divsqrt
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2022-07-14 18:16:00 +00:00 |
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sim-wally
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Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.
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2022-08-27 20:31:09 -07:00 |
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sim-wally-batch
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Renamed endianswap to match module name
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2022-10-04 17:33:49 +00:00 |
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testfloat.do
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Moved fpu modules into subdirectories
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2022-09-20 04:12:05 -07:00 |
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wally-harvard.do
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Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
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2022-01-13 22:21:43 -06:00 |
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wally-pipelined-batch.do
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Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults.
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2022-10-11 10:47:13 -05:00 |
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wally-pipelined.do
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Sort of solved the bit width warning for dtim, irom ranges.
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2022-10-19 10:42:19 -05:00 |
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wave-all.do
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Added generate around uncore.
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2022-08-25 10:35:24 -05:00 |
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wave-fpu.do
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Removed unused FPU waves
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2022-10-14 17:33:32 -07:00 |
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wave.do
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Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks.
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2022-10-23 13:46:50 -05:00 |
