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cvw/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege
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David Harris 1c1acc467e Tweaked SPI to avoid breaking VCS, but the SCLK divider still doesn't produce the right frequency and SCLKenableEarly looks like it wouldn't work for SckDiv = 0
2024-10-26 02:01:09 -07:00
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references Tweaked SPI to avoid breaking VCS, but the SCLK divider still doesn't produce the right frequency and SCLKenableEarly looks like it wouldn't work for SckDiv = 0 2024-10-26 02:01:09 -07:00
src Updated email address authorship for my files. 2024-10-15 10:27:53 -05:00