David Harris e1ad732178 SRT Division unsigned passing Imperas tests		2021-09-30 12:17:24 -04:00
..
slack-notifier
wave-dos	fixed bug where M mode was sensitive to S mode traps	2021-09-07 19:14:39 -04:00
linux-wave.do	Fixed the amo on dcache miss cpu stall issue.	2021-09-17 22:15:03 -05:00
regression-wally.py	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-09-15 17:31:11 -04:00
run_sim.sh
sim-buildroot
sim-buildroot-batch
sim-busybear
sim-busybear-batch
sim-wally
sim-wally-arch-batch	Lint cleaning, riscv-arch-test testing	2021-09-09 11:05:12 -04:00
sim-wally-arch-batch-rv32ic	Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64	2021-09-13 12:40:40 -04:00
sim-wally-batch
sim-wally-batch-muldiv
sim-wally-batch-rv32ic
sim-wally-batch-rv32icfd
sim-wally-batch-rv64icfd
sim-wally-muldiv
sim-wally-rv32ic
sim-wally-rv32icfd
sim-wally-rv64icfd
udiv.c
wally-arch.do	Cleaned up wally-arch test scripts	2021-09-13 00:02:32 -04:00
wally-buildroot-batch.do
wally-buildroot.do	restore functionality of being able to turn on waves at a certain instruction count; restore linux-waves.do because wave.do seems to be in disrepair	2021-09-04 19:45:04 -04:00
wally-busybear-batch.do
wally-busybear.do
wally-coremark_bare.do
wally-pipelined-batch-muldiv.do
wally-pipelined-batch-rv32icfd.do
wally-pipelined-batch-rv64icfd.do
wally-pipelined-batch.do
wally-pipelined-muldiv.do
wally-pipelined-ross.do	Updated Dcache to fully support flush. This appears to work.	2021-09-17 10:25:21 -05:00
wally-pipelined-rv32icfd.do
wally-pipelined-rv64icfd.do
wally-pipelined.do	SRT Division unsigned passing Imperas tests	2021-09-30 12:17:24 -04:00
wally-privileged.do
wave-all.do
wave.do	Finished adding the d cache flush. Required ensuring the write data, address, and size are	2021-09-17 13:03:04 -05:00