Rose Thompson 386cf3eb56 Merge pull request #493 from stineje/main ... marchid approved by RISC-V		2023-11-21 08:33:07 -08:00
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csr.sv	Removed other unused signals from Verilog	2023-11-20 23:37:56 -08:00
csrc.sv	Fixed bug with performance counters not tracking the correct number of requested icache and dcache memory operations.	2023-07-14 16:31:44 -05:00
csri.sv	Improved testing of csri with priv.S	2023-08-24 18:39:15 -07:00
csrm.sv	Update marchid/mvendorid for CV-Wally	2023-11-21 09:23:02 -06:00
csrs.sv	Removed other unused signals from Verilog	2023-11-20 23:37:56 -08:00
csrsr.sv	Removed QEMU from configurations.	2023-07-19 10:23:55 -05:00
csru.sv	Update csru.sv	2023-06-12 20:21:55 -07:00
privdec.sv	Removed other unused signals from Verilog	2023-11-20 23:37:56 -08:00
privileged.sv	Removed other unused signals from Verilog	2023-11-20 23:37:56 -08:00
privmode.sv	Update privmode.sv	2023-06-12 20:27:48 -07:00
privpiperegs.sv	The privileged unit is parameterized using Lim's method.	2023-05-26 12:03:46 -05:00
trap.sv	Updated comments about Interrupt and wfi.	2023-10-26 12:24:36 -05:00