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96 lines
3.5 KiB
Systemverilog
96 lines
3.5 KiB
Systemverilog
///////////////////////////////////////////
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// DCacheMem (Memory for the Data Cache)
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//
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// Written: ross1728@gmail.com July 07, 2021
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// Implements the data, tag, valid, dirty, and replacement bits.
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//
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// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26)
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(input logic clk,
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input logic reset,
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input logic [$clog2(NUMLINES)-1:0] Adr,
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input logic [$clog2(NUMLINES)-1:0] WAdr, // write address for valid and dirty only
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input logic WriteEnable,
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input logic [BLOCKLEN/`XLEN-1:0] WriteWordEnable,
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input logic TagWriteEnable,
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input logic [BLOCKLEN-1:0] WriteData,
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input logic [TAGLEN-1:0] WriteTag,
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input logic SetValid,
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input logic ClearValid,
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input logic SetDirty,
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input logic ClearDirty,
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output logic [BLOCKLEN-1:0] ReadData,
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output logic [TAGLEN-1:0] ReadTag,
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output logic Valid,
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output logic Dirty
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);
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logic [NUMLINES-1:0] ValidBits, DirtyBits;
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genvar words;
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generate
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for(words = 0; words < BLOCKLEN/`XLEN; words++) begin : word
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sram1rw #(.DEPTH(`XLEN),
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.WIDTH(NUMLINES))
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CacheDataMem(.clk(clk),
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.Addr(Adr),
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.ReadData(ReadData[(words+1)*`XLEN-1:words*`XLEN]),
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.WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
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.WriteEnable(WriteEnable & WriteWordEnable[words]));
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end
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endgenerate
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sram1rw #(.DEPTH(TAGLEN),
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.WIDTH(NUMLINES))
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CacheTagMem(.clk(clk),
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.Addr(Adr),
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.ReadData(ReadTag),
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.WriteData(WriteTag),
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.WriteEnable(TagWriteEnable));
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always_ff @(posedge clk, posedge reset) begin
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if (reset)
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ValidBits <= {NUMLINES{1'b0}};
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else if (SetValid & WriteEnable) ValidBits[WAdr] <= 1'b1;
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else if (ClearValid & WriteEnable) ValidBits[WAdr] <= 1'b0;
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Valid <= ValidBits[Adr];
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end
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always_ff @(posedge clk, posedge reset) begin
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if (reset)
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DirtyBits <= {NUMLINES{1'b0}};
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else if (SetDirty & WriteEnable) DirtyBits[WAdr] <= 1'b1;
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else if (ClearDirty & WriteEnable) DirtyBits[WAdr] <= 1'b0;
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Dirty <= DirtyBits[Adr];
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end
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endmodule // DCacheMemWay
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