Ross Thompson 511c36fb1b Improved address bus names and usages in the walker, dcache, and tlbs. ... Merge branch 'walkerEnhance' into main		2021-07-21 14:55:09 -05:00
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cache-sram.sv
cacheLRU.sv	4 way set associative is now working.	2021-07-21 14:01:14 -05:00
dcache.sv	Improved address bus names and usages in the walker, dcache, and tlbs.	2021-07-21 14:55:09 -05:00
DCacheMem.sv	Progress towards the test bench flush.	2021-07-12 14:22:13 -05:00
dmapped.sv
icache.sv	Parameterized I$/D$ configurations and added sanity check assertions in testbench	2021-07-20 08:57:13 -04:00
ICacheCntrl.sv	Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented.	2021-07-09 15:16:38 -05:00
ICacheMem.sv	Partial implementation of the data cache. Missing the fsm.	2021-07-07 17:52:16 -05:00
sram1rw.sv	change sram1rw to have a small delay so that we don't have signals changing on clock edges	2021-07-19 11:30:07 -04:00