5 Commits

Author	SHA1	Message	Date
Ross Thompson	8ca8b9075d	Progress towards the test bench flush.	2021-07-12 14:22:13 -05:00
Ross Thompson	0a6c86af94	Write Hits and Write Misses without eviction are working correctly! The next ... step is to add eviction of dirty lines.	2021-07-10 10:56:25 -05:00
Ross Thompson	7e98610651	Design loads in modelsim, but trap is an X.	2021-07-09 15:37:16 -05:00
Ross Thompson	6abd23a61d	Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented. ... Also faults and the dcache ptw interlock are not implemented.	2021-07-09 15:16:38 -05:00
Ross Thompson	adcc7afffa	Partial implementation of the data cache. Missing the fsm.	2021-07-07 17:52:16 -05:00