Ross Thompson 3fb0a13fe2 Moved other SRAMs to generic/mem.		2022-09-21 12:36:03 -05:00
..
cache.sv	Optimization. Able to remove hptw address muxes from the E stage.	2022-09-08 15:51:18 -05:00
cachefsm.sv	pipelining of fetch into evict AHB requests.	2022-09-13 17:51:55 -05:00
cachereplacementpolicy.sv
cacheway.sv	Merged together bram1p1rw with sram1p1rw as sram1p1rw.	2022-09-21 12:20:00 -05:00
subcachelineread.sv	Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.	2022-08-01 21:08:14 -05:00
ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v