David Harris 6ba3ae662f Merge branch 'main' of https://github.com/openhwgroup/cvw into dev		2023-12-17 19:04:50 -08:00
..
common	Fixed Linux makefile; load branch predictor RAMs at startup for sim; fixed comment in trap; starting to make testbench more compatible with Verilator	2023-12-13 11:33:59 -08:00
fp	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00
sdc	Towards removing the FPGA config file.	2023-11-13 17:20:26 -06:00
testbench-fp.sv	Fix issue with running all and then going from one operand width to another. Issue is due to signals resolving between sizes. I did not catch it before because I did not run through the complete exhaustive tests. This time, went through all tests and tested all the data sizes.	2023-12-17 20:55:06 -06:00
testbench-imperas.sv	Added SPI support to Imperas testbenches	2023-12-07 09:44:31 -08:00
testbench-linux-imperas.sv	Added SPI support to Imperas testbenches	2023-12-07 09:44:31 -08:00
testbench-linux.sv	Testbench fixes to add SPI and make string pp static in testbench.fp to solve compiler issue	2023-11-04 20:36:05 -07:00
testbench-xcelium.sv	Testbench fixes to add SPI and make string pp static in testbench.fp to solve compiler issue	2023-11-04 20:36:05 -07:00
testbench.sv	Use riscv-arch-test arch32e instead of outdated wally-riscv-arch-test wally32e	2023-12-15 05:05:53 -08:00
tests-fp.vh	Update testbench-fp to run TestFloat for all FP operations	2023-04-11 22:16:20 -05:00
tests.vh	Switched to using riscv-arch-test rv32e_m suite. Need to rename it from rv32e_unratified (PR pending)	2023-12-15 19:26:50 -08:00
wallywrapper.sv	Verilator improvements	2023-11-04 03:21:07 -07:00