David Harris d6b8a5e595 hptw: Unified PageTableEntryM and PageTableEntryF outputs of pagetablewalker into PTE		2021-07-17 14:48:44 -04:00
..
adrdec.sv	Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations.	2021-06-24 19:59:29 -04:00
adrdecs.sv	Fixed adrdecs to use Access signals for TIMs	2021-07-05 23:42:58 -04:00
decoder.sv	remove redundant decodes, fixed mmu logic ins/outs	2021-06-07 19:23:30 -04:00
mmu.sv	Fixed walker fault interaction with dcache.	2021-07-16 12:22:13 -05:00
pagetablewalker.sv	hptw: Unified PageTableEntryM and PageTableEntryF outputs of pagetablewalker into PTE	2021-07-17 14:48:44 -04:00
pmachecker.sv	Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.	2021-07-15 11:56:35 -05:00
pmpadrdec.sv	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
pmpchecker.sv	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
tlb.sv	Array of muxes in tlbmixer; abbreviated PPN and VPN to match diagram	2021-07-08 16:58:11 -04:00
tlbcam.sv	Replaced .or with or_rows structural code in MMU read circuitry for synthesis.	2021-07-13 09:32:02 -04:00
tlbcamline.sv	Array of muxes in tlbmixer; abbreviated PPN and VPN to match diagram	2021-07-08 16:58:11 -04:00
tlbcontrol.sv	Simplified tlbmixer mux to and-or	2021-07-08 23:34:24 -04:00
tlblru.sv	Fixed missing stall in InstrRet counter	2021-07-08 20:08:04 -04:00
tlbmixer.sv	added missing tlbmixer.sv	2021-07-09 19:18:23 -04:00
tlbpriority.sv	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
tlbram.sv	Replaced .or with or_rows structural code in MMU read circuitry for synthesis.	2021-07-13 09:32:02 -04:00
tlbramline.sv	Eliminate reserved bits from TLB RAM	2021-07-08 17:35:00 -04:00