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53 lines
2.2 KiB
Systemverilog
53 lines
2.2 KiB
Systemverilog
///////////////////////////////////////////
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// adrdec.sv
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//
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// Written: David_Harris@hmc.edu 29 January 2021
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// Modified:
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//
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// Purpose: Address decoder
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module adrdec (
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input logic [`PA_BITS-1:0] PhysicalAddress,
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input logic [`PA_BITS-1:0] Base, Range,
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input logic Supported,
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input logic AccessValid,
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input logic [1:0] Size,
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input logic [3:0] SizeMask,
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output logic Sel
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);
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logic Match;
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logic SizeValid;
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// determine if an address is in a range starting at the base
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// for example, if Base = 0x04002000 and range = 0x00000FFF,
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// then anything address between 0x04002000 and 0x04002FFF should match (HSEL=1)
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assign Match = &((PhysicalAddress ~^ Base) | Range);
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// determine if legal size of access is being made (byte, halfword, word, doubleword)
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assign SizeValid = SizeMask[Size];
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assign Sel = Match && Supported && AccessValid && SizeValid;
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endmodule
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