..
coverage
Reorganizing sim directory for multiple simulators
2024-04-05 18:19:46 -07:00
coverage-exclusions-rv64gc.do
Fixed merge conflict bug in the last pull request.
2024-04-16 10:32:24 -05:00
fpga-wave.do
Moved do files into questa
2024-04-05 18:42:48 -07:00
GetLineNum.do
Moved do files into questa
2024-04-05 18:42:48 -07:00
imperas.ic
Got imperasDV running linux simulation again.
2024-05-13 16:43:13 -05:00
run-imperas-linux.sh
temporary commit to help debug merging testbench.sv with testbench-imperas.sv
2024-05-17 12:36:00 -05:00
sim-imperas
Reorganizing sim directory for multiple simulators
2024-04-05 18:19:46 -07:00
sim-testfloat
Got the separation of the -G and +variable arguments in the questa do file.
2024-04-06 18:04:48 -05:00
sim-testfloat-batch
Added GUI support and removed unused wave files
2024-04-06 13:43:06 -07:00
sim-testfloat-verilator
Updated sim-testfloat-verilator to use wsim
2024-05-10 05:03:24 -07:00
sim-wally
Updated sim-wally to work with new run scripts.
2024-04-06 16:32:07 -05:00
sim-wally-batch
Removed unnecessary display from testbench.
2024-04-06 16:10:18 -05:00
wally-imperas-cov.do
Still don't understand why wally.do can't load testbench.sv with functional coverage. But wally-imperas-cov.do can load testbench.sv with functional coverage.
2024-05-28 13:00:17 -05:00
wally-imperas-no-idv.do
Moved do files into questa
2024-04-05 18:42:48 -07:00
wally-imperas.do
Moved do files into questa
2024-04-05 18:42:48 -07:00
wally.do
Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.
2024-07-19 17:08:47 -05:00
wave-fpu.do
testfloat running through wsim; moved lint, regression, wsim to bin directory so we don't need ./
2024-04-06 08:22:39 -07:00
wave.do
Modified names so they don't conflict with FPGA's axi signals.
2024-05-24 16:38:47 -05:00
9471dcd296