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debug
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Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.
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2022-10-24 15:38:39 -05:00 |
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bootrom.txt
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Added bootrom.txt.
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2022-03-30 17:29:48 -05:00 |
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insert_debug_comment.sh
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Maded insert_debug_comment.sh compatible with cygwin.
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2024-04-22 10:48:34 -05:00 |
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Makefile
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Fixed fpga to work with the updated regression changes.
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2024-04-22 10:42:01 -05:00 |
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probe
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Update python shebangs to use /usr/bin/env python3 so virtual environment can be used (also aids in general portability)
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2024-07-03 20:42:55 -07:00 |
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wally.tcl
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The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file.
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2024-05-30 15:48:27 -05:00 |
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wave_config.wcfg
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Updateds to vcu118 constraints and device tree.
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2023-08-02 16:51:32 -05:00 |
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xlnx_ahblite_axi_bridge.tcl
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Added more support for Arty A7 board.
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2023-04-10 16:01:17 -05:00 |
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xlnx_axi_clock_converter.tcl
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Added more support for Arty A7 board.
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2023-04-10 16:01:17 -05:00 |
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xlnx_axi_crossbar.tcl
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The Vivado-RISC-V SDC works. Wally is now booting through it.
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2023-05-26 15:42:33 -05:00 |
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xlnx_axi_dwidth_conv_32to64.tcl
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Connected the axi_sdc_controller with an axi crossbar.
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2023-01-13 13:56:01 -06:00 |
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xlnx_axi_dwidth_conv_64to32.tcl
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Connected the axi_sdc_controller with an axi crossbar.
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2023-01-13 13:56:01 -06:00 |
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xlnx_axi_dwidth_converter.tcl
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Connected the axi_sdc_controller with an axi crossbar.
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2023-01-13 13:56:01 -06:00 |
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xlnx_axi_prtcl_conv.tcl
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Modified makefile. Added axi protocol converter IP.
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2023-01-23 19:30:29 -06:00 |
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xlnx_ddr3-artya7-mig.prj
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It's almost working.
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2023-04-18 14:24:59 -05:00 |
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xlnx_ddr3-ArtyA7.tcl
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Finally fixed the ddr3 mig script to work correclty.
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2023-04-14 11:41:51 -05:00 |
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xlnx_ddr4-vcu108.tcl
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Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.
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2022-10-24 15:38:39 -05:00 |
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xlnx_ddr4-vcu118.tcl
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Pushed vcu118 to 71MHz.
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2023-08-25 17:04:50 -05:00 |
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xlnx_ddr4.tcl
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Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.
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2022-10-24 15:38:39 -05:00 |
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xlnx_mmcm.tcl
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Reduced Arty A7 clock speed to 20Mhz to support Zicclsm.
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2023-11-13 16:44:02 -06:00 |
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xlnx_proc_sys_reset.tcl
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Added more support for Arty A7 board.
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2023-04-10 16:01:17 -05:00 |
