Rose Thompson 9471dcd296 Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes. ... Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.		2024-07-19 17:08:47 -05:00
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checksignature.sv	Significant refactoring of testbench.	2023-06-14 17:02:49 -05:00
DCacheFlushFSM.sv	script cleanup	2024-04-20 17:22:31 -07:00
functionName.sv	Changed '0 to 0 where possible per Chapter 4 style guidelines	2024-03-06 05:48:17 -08:00
instrNameDecTB.sv	Eliminate more logical operators and replace with bitwise	2024-05-15 10:50:23 -07:00
instrTrackerTB.sv	moved riscvassertons to its own file, added proper license headers to testbench support files	2023-02-16 19:40:27 -08:00
loggers.sv	Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.	2024-07-19 17:08:47 -05:00
ramxdetector.sv	Yay! I got verilator to compile our testbench! Does it actually work I don't know.	2023-12-18 16:44:34 -06:00
riscvassertions.sv	Certain Zcb instructions are dependent on other extensions, not the entire extension	2024-05-15 19:16:43 -07:00
wallyTracer.sv	Removed unused signals from WallyTracer	2024-04-30 08:54:28 -07:00
watchdog.sv	Changed '0 to 0 where possible per Chapter 4 style guidelines	2024-03-06 05:48:17 -08:00