Ross Thompson
f1781c6bc8
More cachefsm cleanup.
2022-02-07 10:54:22 -06:00
Ross Thompson
b89ce18473
Cache cleanup.
2022-02-07 10:43:58 -06:00
Ross Thompson
6f4a321d31
More cachfsm cleanup.
2022-02-07 10:33:50 -06:00
David Harris
60c3cdad3a
Reverted cache change
2022-02-07 14:47:20 +00:00
David Harris
c21eb67a07
Cache syntax cleanup
2022-02-07 14:43:24 +00:00
Ross Thompson
8bcaadda6b
More cachefsm cleanup.
2022-02-06 21:50:44 -06:00
Ross Thompson
347e9228f8
started cachefsm cleanup.
2022-02-06 21:39:38 -06:00
Ross Thompson
308cc34d6f
Added config to allow using the save/restore or replay implementation to handle sram clocked read delay.
2022-02-04 23:49:07 -06:00
Ross Thompson
1766c0f5ba
Removed unused ports from caches and buses.
2022-02-04 22:52:51 -06:00
Ross Thompson
c846368537
Moved the sub cache line read logic to lsu/ifu.
2022-02-04 20:42:53 -06:00
Ross Thompson
f6f0539e10
Got separate module for the sub cache line read.
2022-02-04 20:23:09 -06:00
Ross Thompson
ceb2cc30b9
Second optimization of save/restore.
2022-02-04 14:35:12 -06:00
Ross Thompson
498c2b589a
Optimization of cache save/restore.
2022-02-04 14:21:04 -06:00
Ross Thompson
83fdedcec6
Working first cut of the cache changes moving the replay to a save/restore.
...
The current implementation is too expensive costing (tag+linelen)*numway flip flops and muxes.
2022-02-04 13:31:32 -06:00
David Harris
c3122ce214
sram1rw cleanup
2022-02-03 18:03:22 +00:00
David Harris
0e1d784b60
sram1rw cleanup
2022-02-03 17:50:23 +00:00
David Harris
eb8dd5e7d7
cachereplacementpolicy cleanup
2022-02-03 17:19:14 +00:00
David Harris
5f7326368e
cachereplacementpolicy cleanup
2022-02-03 17:18:48 +00:00
David Harris
9b6a4d1d52
cacheway cleanup
2022-02-03 16:52:22 +00:00
David Harris
7a8cc5ef21
cacheway cleanup
2022-02-03 16:33:01 +00:00
David Harris
0fbc32204c
cacheway cleanup
2022-02-03 16:07:55 +00:00
David Harris
c22f7eb11c
cacheway cleanup
2022-02-03 16:00:57 +00:00
David Harris
e92461159d
cache cleanup
2022-02-03 15:36:11 +00:00
Ross Thompson
23c4ba2777
1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.
...
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
2022-01-26 18:23:39 -06:00
David Harris
b967bcede2
LSU Cleanup
2022-01-15 01:11:17 +00:00
David Harris
3d2671a8b0
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
David Harris
8481c93e1b
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-07 05:39:16 +00:00
David Harris
261882bf78
Used .* in wrapper
2022-01-07 05:23:42 +00:00
Ross Thompson
fa0080ca70
Modified the mmu to not mux the lower 12 bits of the physical address and instead directly
...
assign from the input non translated virtual address. Since the lower bits never change there is
no reason to place these lower bits on a longer critical path.
The cache and lsu were previously using the lower bits from the virtual address rather than
the physical address. This change will allow us to keep the shorter critical path and
reduce the complexity of the lsu, ifu, and cache drawings.
2022-01-06 23:19:09 -06:00
Ross Thompson
0438975e27
Minor optimization to cache replacement.
2022-01-06 17:19:14 -06:00
Ross Thompson
e0740034f0
Clean up of cachefsm.
2022-01-06 16:32:49 -06:00
Ross Thompson
f604a0d79e
cleaned up cacheway and sram1rw.sv. also noticed possible bug in sram1rw.sv.
2022-01-05 22:56:18 -06:00
Ross Thompson
a4afc1bc54
More name cleanup in cache.
2022-01-05 22:37:53 -06:00
Ross Thompson
e74e8c2e86
Changed names of address in caches.
...
Removed old cache files.
2022-01-05 22:19:36 -06:00
Ross Thompson
da585b30f9
Slower but correct implementation of flush.
2022-01-05 16:57:22 -06:00
Ross Thompson
7086a0ed08
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-05 14:15:27 -06:00
Ross Thompson
cc51a27a34
Fixed bug with flush dirty not cleared in the correct cache line.
2022-01-05 14:14:01 -06:00
David Harris
6d4714651c
Removed more generate statements
2022-01-05 16:25:08 +00:00
David Harris
da5ead23bf
Removed more generate statements
2022-01-05 16:01:03 +00:00
Ross Thompson
98be8201b2
Renamed most signals inside cache.sv so they are agnostic to i or d.
2022-01-04 23:52:42 -06:00
Ross Thompson
fffaf654e6
the i and d caches now share common verilog.
2022-01-04 23:40:37 -06:00
Ross Thompson
13dbf3cc0f
parameterized the caches with the goal of using common rtl for both i and d caches.
2022-01-04 22:40:51 -06:00
Ross Thompson
888a60d8d6
Switched block for line in caches.
2022-01-04 22:08:18 -06:00
Ross Thompson
cb301a78ad
Fixed bug where last line of dcache was not written back to memory on dcache flush.
2022-01-04 21:55:48 -06:00
Ross Thompson
ecc7bf5237
Fixed dcache flush.
2022-01-04 18:40:58 -06:00
David Harris
d1a7416028
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-04 19:47:51 +00:00
David Harris
115287adc8
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
