David Harris
ea805d32ec
Removed QEMU from UART
2023-06-14 08:39:01 -07:00
Harshini Srinath
629ccb191f
Update csrs.sv
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Program clean up
2023-06-13 22:16:43 -07:00
Harshini Srinath
49c84f888f
Update csrm.sv
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2023-06-13 22:08:06 -07:00
Harshini Srinath
aff15a0a46
Update csrc.sv
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2023-06-13 21:54:47 -07:00
Harshini Srinath
fb019a736c
Update csr.sv
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2023-06-13 21:12:49 -07:00
harshini
17724f7832
deleting CodeAligner file
2023-06-13 17:41:37 -07:00
Harshini Srinath
58c617c548
Update ahbapbbridge.sv
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2023-06-12 20:49:46 -07:00
Harshini Srinath
475e11e03f
Update trap.sv
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2023-06-12 20:31:44 -07:00
Harshini Srinath
e2af1fabd2
Update privmode.sv
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2023-06-12 20:27:48 -07:00
Harshini Srinath
ac7043770d
Update privileged.sv
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2023-06-12 20:26:07 -07:00
Harshini Srinath
5f7fe5619b
Update csru.sv
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2023-06-12 20:21:55 -07:00
Harshini Srinath
8487a82efd
Update csrsr.sv
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2023-06-12 20:19:47 -07:00
Harshini Srinath
32ba95a88f
Update csrsr.sv
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2023-06-12 20:15:29 -07:00
Harshini Srinath
8c902a3ec2
Update csrs.sv
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2023-06-12 19:53:41 -07:00
Harshini Srinath
5906b5e729
Update csrm.sv
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2023-06-12 19:42:45 -07:00
Harshini Srinath
f7522ad53c
Update csri.sv
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2023-06-12 19:32:04 -07:00
Harshini Srinath
7dc1595ccc
Update csrc.sv
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2023-06-12 19:03:34 -07:00
Harshini Srinath
ba23a90e9d
Update csr.sv
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2023-06-12 18:51:37 -07:00
Harshini Srinath
794d080aa3
Update pmpchecker.sv
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2023-06-12 18:44:36 -07:00
Harshini Srinath
5a7ee9f1c0
Update pmpadrdec.sv
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2023-06-12 18:41:47 -07:00
Harshini Srinath
ed1d80e37b
Update pmachecker.sv
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2023-06-12 18:39:36 -07:00
Harshini Srinath
91836a6cf3
Update mmu.sv
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2023-06-12 18:36:04 -07:00
Harshini Srinath
3e969c84c7
Update hptw.sv
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2023-06-12 18:31:38 -07:00
Harshini Srinath
3a8631854f
Update adrdecs.sv
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2023-06-12 18:22:32 -07:00
Harshini Srinath
ace24cb879
Update adrdec.sv
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2023-06-12 17:28:21 -07:00
Harshini Srinath
be09e66ec4
Update mul.sv
2023-06-12 14:00:37 -07:00
Harshini Srinath
e7ef3d2136
Update mdu.sv
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2023-06-12 13:54:54 -07:00
Harshini Srinath
6ad67a8102
Update div.sv
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2023-06-12 13:47:09 -07:00
Harshini Srinath
c394f22803
Update swbytemask.sv
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2023-06-12 13:37:35 -07:00
Harshini Srinath
8af3079f10
Update subwordwrite.sv
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2023-06-12 13:35:27 -07:00
Harshini Srinath
c72d573e94
Update subwordread.sv
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2023-06-12 13:31:54 -07:00
Harshini Srinath
086e1cb2df
Update lsu.sv
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2023-06-12 13:29:18 -07:00
Harshini Srinath
45fde3082e
Update lrsc.sv
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2023-06-12 13:14:36 -07:00
Harshini Srinath
a0c6000138
Update dtim.sv
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2023-06-12 13:11:24 -07:00
Harshini Srinath
7a3c78a80d
Update atomic.sv
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2023-06-12 13:08:54 -07:00
Harshini Srinath
70b6d01d2e
Update amoalu.sv
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2023-06-12 12:54:50 -07:00
Harshini Srinath
a53cdbd166
Update spill.sv
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2023-06-12 12:50:11 -07:00
Harshini Srinath
7fa3b87275
Update irom.sv
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2023-06-12 12:44:09 -07:00
Harshini Srinath
128e88a7a0
Update ifu.sv
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2023-06-12 12:38:52 -07:00
Harshini Srinath
e2a9e257c7
Update decompress.sv
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2023-06-12 12:27:55 -07:00
Harshini Srinath
a849fa78cb
Update CodeAligner.py
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2023-06-12 12:25:47 -07:00
Harshini Srinath
80289a1b67
Update shifter.sv
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2023-06-12 12:23:45 -07:00
Harshini Srinath
201d61c575
Update regfile.sv
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2023-06-12 12:21:25 -07:00
Harshini Srinath
055e41bc42
Update ieu.sv
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2023-06-12 12:19:04 -07:00
Harshini Srinath
f5a77be56f
Update extend.sv
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2023-06-12 12:15:33 -07:00
Harshini Srinath
1a59222a08
Update datapath.sv
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2023-06-12 12:13:58 -07:00
Ross Thompson
9a1042b0b1
This parameterizes the testbench but does not use the verilator updates or the new testbench.
2023-06-12 11:00:30 -05:00
Ross Thompson
e5bae37b0b
Merge pull request #327 from harshinisrinath1001/main
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Fixed the spacing in the fpu module
2023-06-12 11:53:52 -04:00
Harshini Srinath
ea0199b3a6
Update prioritythermometer.sv
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2023-06-11 19:18:21 -07:00
Harshini Srinath
8951f965fb
Update or_rows.sv
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2023-06-11 19:16:37 -07:00
Harshini Srinath
aec1330986
Update neg.sv
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2023-06-11 19:15:28 -07:00
Harshini Srinath
0a08da2daf
Update counter.sv
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2023-06-11 19:12:57 -07:00
Harshini Srinath
6c76ca1fef
Update adder.sv
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2023-06-11 19:09:18 -07:00
Harshini Srinath
420ee8dad9
Update unpackinput.sv
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2023-06-11 17:09:11 -07:00
Harshini Srinath
7e0dedea19
Update fctrl.sv
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2023-06-11 17:03:29 -07:00
Harshini Srinath
3bc164a4ca
Update fcmp.sv
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2023-06-11 16:54:52 -07:00
Harshini Srinath
74fa15bcb4
Update fsgninj.sv
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2023-06-11 16:52:00 -07:00
Harshini Srinath
2739ea26a7
Update fregfile.sv
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2023-06-11 16:49:20 -07:00
Harshini Srinath
7770f7e79b
Update fpu.sv
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2023-06-11 16:43:31 -07:00
Harshini Srinath
ca170c8b81
Update fhazard.sv
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2023-06-11 16:06:44 -07:00
Harshini Srinath
d9b58c44cf
Update fcvt.sv
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2023-06-11 16:05:14 -07:00
Harshini Srinath
21015c8e4a
Update fcvt.sv
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2023-06-11 15:59:20 -07:00
Ross Thompson
1bf57e3dd1
Merge branch 'verilator'
2023-06-11 15:28:04 -05:00
David Harris
a192214f86
Fixed lint errors, presumably detected by latest version of verilator
2023-06-11 06:48:42 -07:00
David Harris
d5b237e728
Merge pull request #322 from harshinisrinath1001/main
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Fixing spacing for ebu
2023-06-11 06:00:35 -07:00
Harshini Srinath
fb1e5e401f
Update fctrl.sv
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2023-06-10 19:38:50 -07:00
Harshini Srinath
71248a7523
Update fcmp.sv
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2023-06-10 19:35:58 -07:00
Harshini Srinath
db2ac9604a
Update fcmp.sv
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2023-06-10 19:34:58 -07:00
Harshini Srinath
02e8689999
Update fclassify.sv
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2023-06-10 19:30:18 -07:00
Harshini Srinath
61ebfdb55f
Update controllerinput.sv
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2023-06-10 18:26:06 -07:00
Harshini Srinath
a90bbba617
Update ahbinterface.sv
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2023-06-10 18:18:16 -07:00
Harshini Srinath
2f47a6e04f
Program clean up
2023-06-10 18:13:40 -07:00
Ross Thompson
d6681b5342
Merge pull request #319 from davidharrishmc/dev
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Renamed Performance Counter extension
2023-06-09 21:21:45 -04:00
David Harris
b15c5e2a51
Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare
2023-06-09 14:40:01 -07:00
David Harris
e2e6f6f255
Added named support for Zicntr and Zihpm
2023-06-09 09:35:51 -07:00
Harshini Srinath
107ebf6a3c
Update ebu.sv
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Code clean up
2023-06-09 08:53:27 -07:00
Harshini Srinath
b4e5f43acb
Update subcachelineread.sv
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Code clean up
2023-06-09 08:50:51 -07:00
Harshini Srinath
7475a0eeed
Update cacheway.sv
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Code clean up
2023-06-09 08:48:11 -07:00
Harshini Srinath
fcac659e34
Update cacheLRU.sv
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Code clean up
2023-06-09 08:43:38 -07:00
Harshini Srinath
1f1fcce062
Update cache.sv
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Formatting clean up
2023-06-09 08:39:57 -07:00
Ross Thompson
9bae203d1c
Updated parameterization types. Modelsim version 2022.1 did requires defaults to a 32 bit integer. The base and ranges for the address decoder need to be larger.
2023-06-09 09:28:24 -05:00
David Harris
62a8332c8f
Merge pull request #313 from ross144/main
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Fix extraneous force in testbench which keep btb in reset.
2023-06-06 08:41:34 -07:00
David Harris
df212ce7d8
Merge pull request #312 from ross144/main
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Fixed typo in coremark makefile.
2023-06-06 05:44:22 -07:00
Ross Thompson
822e60bd3d
Found the coremark performance issue. The testbench was continuously forcing the BTB to all zeros. Once fixed it resolved the performance problem.
2023-06-05 15:42:05 -05:00
James Stine
51d77b0414
Update some spacing to make it look better
2023-06-05 11:03:06 -05:00
Ross Thompson
80cdb02d43
Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet.
2023-05-31 16:51:00 -05:00
Ross Thompson
e56497101a
Updated source code to be compatible with verilator 5.011 for lint only.
2023-05-31 10:44:23 -05:00
Ross Thompson
ab91fe7436
Cleanup parameterization for verilator 5.010.
2023-05-31 10:02:34 -05:00
Ross Thompson
3c94c186db
Possible fix for Linux bug and bug 203. ImperasDV mismatches in linux boot around 571M instructions after the login prompt.
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This bug occurs when there are back to back HPTW requests and the first generates an access fault during the walk. The old implementation uses a delayed version of the fault to prevent the HTPW fsm from transitioning out of the IDLE state. Because the first request generates the fault and the second request is pipelined the second request appears as if it also faults so the FSM does not perform the walk.
The new implementation adds a FAULT state. When the HPTW generates an access fault it transitions to this state removes the HPTWStall and then transitions to IDLE. There may still be a remaining bug here if the pipeline is stalled for another reason. However I don't think it is possible by construction. The only possible sources of stalls at this point would be IFU and LSU stalls and both are required to make this condition happen.
2023-05-30 15:20:24 -05:00
Ross Thompson
903f2f9063
Merge branch 'param-lim-merge'
2023-05-26 16:25:35 -05:00
Ross Thompson
b8474b208e
Uncore is now parameterized.
2023-05-26 16:24:12 -05:00
Ross Thompson
340aac0934
Got the branch predictor parameterized using Lim's method. Also had to add a global enum included in both cvw.sv and the configs which defines the branch predictor types. This should be synthesizable, but I'll need to double check.
2023-05-26 16:00:14 -05:00
Jacob Pease
2ad9c72acc
The Vivado-RISC-V SDC works. Wally is now booting through it.
2023-05-26 15:42:33 -05:00
Ross Thompson
e6d25b7f70
Finished fpu parameterization using Lim's method.
2023-05-26 14:40:06 -05:00
Ross Thompson
ef2bb7df93
fdiv is now parameterized using Lim's method.
2023-05-26 14:25:14 -05:00
Ross Thompson
c76eb315bc
Parameterized fpu's unpack and fma using Lim's method.
2023-05-26 14:12:25 -05:00
Ross Thompson
923c00b928
I think I've solved the slow down issue. Parameters can't be mixed with cvw_t and other types.
2023-05-26 13:56:51 -05:00
Ross Thompson
8aba897386
Update top level parameterized. Simulation slowed down to 4.5 minutes.
2023-05-26 12:13:11 -05:00
Ross Thompson
d47951fb51
The privileged unit is parameterized using Lim's method.
2023-05-26 12:03:46 -05:00
Ross Thompson
dd7c7f0a39
Completed LSU parameterization based on Lim's changes.
2023-05-26 11:26:09 -05:00
Ross Thompson
0c2a54540b
Subwordread now parameterized.
2023-05-26 11:22:44 -05:00
Ross Thompson
3765ebfb9f
PMA checker's address decoder is now parameterized. I did not see bit slicing in Lim's code. I'm not sure how they got around this issue.
2023-05-26 11:06:48 -05:00
Ross Thompson
60bcd3d21a
Progress on LSU.
2023-05-26 10:47:09 -05:00
Ross Thompson
7c364d5a77
Updated mmu's tlb and hptw to use Lim's parameterization.
2023-05-24 18:02:22 -05:00
Ross Thompson
438c955d1c
PM(P/A) checkers parameterized based on Lim's work.
2023-05-24 17:20:55 -05:00
Ross Thompson
febb2442db
Partial parameterization into mmu.
2023-05-24 16:12:41 -05:00
Ross Thompson
7fc53226ac
MDU and hazard unit now also parameterized. Based on Lim's work. Again I want to clarify this their work. Not mine. I'm just doing this because the merge had an issue.
2023-05-24 15:01:35 -05:00
Ross Thompson
8f9151b125
More parameterization. Based on Lim's work. EBU, IFU (except bpred), and IEU done.
2023-05-24 14:56:02 -05:00
Ross Thompson
e33db7f9a7
More parameterization. Copied Lim. Still no slow down.
2023-05-24 14:49:22 -05:00
Ross Thompson
d3123fc00a
Updated a large number of the source files to use parameters rather than `defines. Based on Lim's work. So far there is no simulation slow down.
2023-05-24 14:05:44 -05:00
Ross Thompson
3de3a42f97
Merged changes.
2023-05-24 13:15:52 -05:00
Ross Thompson
b28a75f32a
Updated headers to local branch history predictors.
2023-05-24 12:52:42 -05:00
Ross Thompson
c5aeb08e5c
Trying to figure out why the parameterization slowed down modelsim so much.
2023-05-24 12:44:42 -05:00
Ross Thompson
6163fc29e1
Adds local history predictor.
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Fixes performance counters, but not coremark.
2023-05-23 18:53:46 -05:00
Ross Thompson
1dc7fb567b
Merge branch 'localhistory'
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Repair to wave file.
Created implementations of local history. Part of my Ph.D. research.
2023-05-22 10:13:31 -05:00
Ross Thompson
81b33fb48e
Fixes load and store stall counters.
2023-05-22 10:08:49 -05:00
Ross Thompson
2612ca4062
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-05-11 14:56:53 -05:00
Ross Thompson
03823a9bc1
Partially working local history repair.
2023-05-11 14:56:26 -05:00
Ross Thompson
e34b25511a
Baseline localhistory with speculative repair built.
2023-05-05 15:23:45 -05:00
Ross Thompson
faf71294d6
Fixed bug in local history predictor.
2023-05-04 16:54:41 -05:00
Ross Thompson
e11d42b270
Almost working ahead pipelined local history predictor.
2023-05-04 16:17:31 -05:00
Ross Thompson
8da2b18543
Maybe I finally have the ahead pipelined local history predictor working.
2023-05-04 14:11:34 -05:00
Ross Thompson
afafa9718d
Ahead pipelining is not yet working. :(
2023-05-03 17:41:38 -05:00
Ross Thompson
35a59a1193
I think ahead pipelining is working for local history.
2023-05-03 12:52:32 -05:00
Ross Thompson
c4d6724867
Updated configs for local branch history `defines.
2023-05-02 11:11:04 -05:00
Ross Thompson
9ee6ba8964
Added comment explaining the difference between global history and local history basic implementations.
2023-05-02 11:01:46 -05:00
Ross Thompson
799c25cc60
Swapped the m and k parameters for local history predictor.
2023-05-02 10:52:41 -05:00
Ross Thompson
b9abb2a491
Maybe have the baseline local history predictor working.
2023-05-01 15:45:27 -05:00
Ross Thompson
6e6185743a
Merge branch 'main' into localhistory
2023-05-01 10:35:50 -05:00
David Harris
c1786bfec8
IMMU exclude non word-sized accesses
2023-05-01 08:14:19 -07:00
Ross Thompson
f1038f1eec
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-04-30 23:30:13 -05:00
David Harris
bfa35d727b
Fixed redundant check of SupportedFmt on fmv that caused coverage problem on fctrl
2023-04-29 05:58:40 -07:00
David Harris
d5c350c597
Merged coverage exclusions for PMP
2023-04-28 08:04:25 -07:00
David Harris
ca5a71bbe5
PMA Checker coverage
2023-04-28 07:53:59 -07:00
David Harris
22e4f82a99
Commenting
2023-04-28 07:52:08 -07:00
David Harris
f6f43e826a
Removed clear from TLBLRU because there is no need to flush LRU state and it causes coverage issues
2023-04-28 07:03:46 -07:00
Ross Thompson
253344f491
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-04-27 16:38:36 -05:00
David Harris
e962e95e53
CSR code cleanup
2023-04-27 14:12:57 -07:00
David Harris
e519eaa33f
Renamed byteUnit to byteop
2023-04-27 14:10:46 -07:00
Ross Thompson
8eaa4bf075
Fixed bug in cacheLRU when NUMWAYS = 2.
2023-04-27 14:30:01 -05:00
Liam
6803347a49
Pmpadrdecs test cases changing AdrMode to 2 or 3
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Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] writing values to pmpcfg0 to change AdrMode to 2 or 3
Also exclusion for pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1 in pmpadrdec.sv
2023-04-27 12:23:35 -07:00
David Harris
e69ebc45c0
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-04-27 07:30:07 -07:00
Alexa Wright
667c54c129
Merge branch 'openhwgroup:main' into main
2023-04-26 16:26:30 -07:00
Alexa Wright
79031e3de0
Added better comment for the exclusion in privdec.sv
2023-04-26 16:25:55 -07:00
David Harris
7c1a4e5e32
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-04-26 15:40:11 -07:00
David Harris
0ad5165795
Merge pull request #283 from SydRiley/main
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Resolving unpackinput coverage issue with BadNaNBox, and increasing ifu and lsu coverage% through exclusions
2023-04-26 15:40:01 -07:00
Sydeny
4595c22fe1
Addressing Redundant logic around BadNanBox, fpu coverage from 96.61% to 96.77%
2023-04-26 14:35:43 -07:00
David Harris
d71d84b386
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-04-26 05:53:42 -07:00
Alec Vercruysse
6299c0ef0b
Cacheway Exclude FlushStage=1 when SetValidWay=1
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We determined that this case is not hit even for i$, so this
case is also excluded separately for i$. It could be a better
idea to remove the ~FlushStage check completely (if we're sure).
My reasoning for this one is written as a comment in the exclusion
script: since a pipeline stall is asserted by the cache in the fetch
stage (which happens before going into the WRITE_LINE state and
asserting SetValidWay), there seems to be no way to trigger
a FlushStage (FlushW for D$) while the stallM is active.
2023-04-25 20:30:46 -07:00
Alexa Wright
55a74fd315
Excluded and added coverage for WFI test case.
2023-04-25 17:06:57 -07:00
