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https://github.com/openhwgroup/cvw
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Update hptw.sv
Program clean up
This commit is contained in:
Harshini Srinath
GitHub
parent
3a8631854f
commit
3e969c84c7
118
src/mmu/hptw.sv
118
src/mmu/hptw.sv
@ -30,39 +30,39 @@
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///////////////////////////////////////////
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module hptw import cvw::*; #(parameter cvw_t P) (
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input logic clk, reset,
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input logic clk, reset,
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input logic [P.XLEN-1:0] SATP_REGW, // includes SATP.MODE to determine number of levels in page table
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input logic [P.XLEN-1:0] PCSpillF, // addresses to translate
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input logic [P.XLEN+1:0] IEUAdrExtM, // addresses to translate
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input logic [1:0] MemRWM, AtomicM,
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input logic [1:0] MemRWM, AtomicM,
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// system status
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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input logic [1:0] STATUS_MPP,
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input logic [1:0] PrivilegeModeW,
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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input logic [1:0] STATUS_MPP,
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input logic [1:0] PrivilegeModeW,
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input logic [P.XLEN-1:0] ReadDataM, // page table entry from LSU
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input logic [P.XLEN-1:0] WriteDataM,
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input logic DCacheStallM, // stall from LSU
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input logic [2:0] Funct3M,
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input logic [6:0] Funct7M,
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input logic ITLBMissF,
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input logic DTLBMissM,
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input logic FlushW,
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input logic InstrUpdateDAF,
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input logic DataUpdateDAM,
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input logic DCacheStallM, // stall from LSU
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input logic [2:0] Funct3M,
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input logic [6:0] Funct7M,
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input logic ITLBMissF,
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input logic DTLBMissM,
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input logic FlushW,
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input logic InstrUpdateDAF,
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input logic DataUpdateDAM,
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output logic [P.XLEN-1:0] PTE, // page table entry to TLBs
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output logic [1:0] PageType, // page type to TLBs
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output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry
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output logic [1:0] PreLSURWM,
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output logic [1:0] PageType, // page type to TLBs
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output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry
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output logic [1:0] PreLSURWM,
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output logic [P.XLEN+1:0] IHAdrM,
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output logic [P.XLEN-1:0] IHWriteDataM,
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output logic [1:0] LSUAtomicM,
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output logic [2:0] LSUFunct3M,
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output logic [6:0] LSUFunct7M,
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output logic IgnoreRequestTLB,
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output logic SelHPTW,
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output logic HPTWStall,
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input logic LSULoadAccessFaultM, LSUStoreAmoAccessFaultM,
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output logic LoadAccessFaultM, StoreAmoAccessFaultM, HPTWInstrAccessFaultF
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output logic [1:0] LSUAtomicM,
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output logic [2:0] LSUFunct3M,
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output logic [6:0] LSUFunct7M,
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output logic IgnoreRequestTLB,
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output logic SelHPTW,
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output logic HPTWStall,
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input logic LSULoadAccessFaultM, LSUStoreAmoAccessFaultM,
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output logic LoadAccessFaultM, StoreAmoAccessFaultM, HPTWInstrAccessFaultF
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);
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typedef enum logic [3:0] {L0_ADR, L0_RD,
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@ -72,39 +72,39 @@ module hptw import cvw::*; #(parameter cvw_t P) (
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LEAF, IDLE, UPDATE_PTE,
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FAULT} statetype;
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logic DTLBWalk; // register TLBs translation miss requests
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logic DTLBWalk; // register TLBs translation miss requests
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logic [P.PPN_BITS-1:0] BasePageTablePPN;
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logic [P.PPN_BITS-1:0] CurrentPPN;
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logic Executable, Writable, Readable, Valid, PTE_U;
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logic Misaligned, MegapageMisaligned;
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logic ValidPTE, LeafPTE, ValidLeafPTE, ValidNonLeafPTE;
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logic StartWalk;
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logic TLBMiss;
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logic PRegEn;
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logic [1:0] NextPageType;
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logic Executable, Writable, Readable, Valid, PTE_U;
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logic Misaligned, MegapageMisaligned;
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logic ValidPTE, LeafPTE, ValidLeafPTE, ValidNonLeafPTE;
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logic StartWalk;
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logic TLBMiss;
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logic PRegEn;
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logic [1:0] NextPageType;
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logic [P.SVMODE_BITS-1:0] SvMode;
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logic [P.XLEN-1:0] TranslationVAdr;
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logic [P.XLEN-1:0] NextPTE;
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logic UpdatePTE;
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logic HPTWUpdateDA;
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logic UpdatePTE;
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logic HPTWUpdateDA;
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logic [P.PA_BITS-1:0] HPTWReadAdr;
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logic SelHPTWAdr;
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logic SelHPTWAdr;
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logic [P.XLEN+1:0] HPTWAdrExt;
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logic ITLBMissOrUpdateDAF;
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logic DTLBMissOrUpdateDAM;
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logic LSUAccessFaultM;
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logic ITLBMissOrUpdateDAF;
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logic DTLBMissOrUpdateDAM;
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logic LSUAccessFaultM;
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logic [P.PA_BITS-1:0] HPTWAdr;
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logic [1:0] HPTWRW;
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logic [2:0] HPTWSize; // 32 or 64 bit access
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statetype WalkerState, NextWalkerState, InitialWalkerState;
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logic HPTWLoadAccessFault, HPTWStoreAmoAccessFault, HPTWInstrAccessFault;
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logic HPTWLoadAccessFaultDelay, HPTWStoreAmoAccessFaultDelay, HPTWInstrAccessFaultDelay;
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logic HPTWAccessFaultDelay;
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logic TakeHPTWFault, TakeHPTWFaultDelay;
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logic [1:0] HPTWRW;
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logic [2:0] HPTWSize; // 32 or 64 bit access
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statetype WalkerState, NextWalkerState, InitialWalkerState;
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logic HPTWLoadAccessFault, HPTWStoreAmoAccessFault, HPTWInstrAccessFault;
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logic HPTWLoadAccessFaultDelay, HPTWStoreAmoAccessFaultDelay, HPTWInstrAccessFaultDelay;
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logic HPTWAccessFaultDelay;
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logic TakeHPTWFault, TakeHPTWFaultDelay;
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// map hptw access faults onto either the original LSU load/store fault or instruction access fault
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assign LSUAccessFaultM = LSULoadAccessFaultM | LSUStoreAmoAccessFaultM;
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assign HPTWLoadAccessFault = LSUAccessFaultM & DTLBWalk & MemRWM[1] & ~MemRWM[0];
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assign LSUAccessFaultM = LSULoadAccessFaultM | LSUStoreAmoAccessFaultM;
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assign HPTWLoadAccessFault = LSUAccessFaultM & DTLBWalk & MemRWM[1] & ~MemRWM[0];
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assign HPTWStoreAmoAccessFault = LSUAccessFaultM & DTLBWalk & MemRWM[0];
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assign HPTWInstrAccessFault = LSUAccessFaultM & ~DTLBWalk;
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@ -140,16 +140,16 @@ module hptw import cvw::*; #(parameter cvw_t P) (
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assign ValidNonLeafPTE = ValidPTE & ~LeafPTE;
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if(P.SVADU_SUPPORTED) begin : hptwwrites
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logic ReadAccess, WriteAccess;
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logic InvalidRead, InvalidWrite, InvalidOp;
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logic UpperBitsUnequal;
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logic OtherPageFault;
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logic [1:0] EffectivePrivilegeMode;
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logic ImproperPrivilege;
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logic SaveHPTWAdr, SelHPTWWriteAdr;
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logic ReadAccess, WriteAccess;
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logic InvalidRead, InvalidWrite, InvalidOp;
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logic UpperBitsUnequal;
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logic OtherPageFault;
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logic [1:0] EffectivePrivilegeMode;
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logic ImproperPrivilege;
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logic SaveHPTWAdr, SelHPTWWriteAdr;
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logic [P.PA_BITS-1:0] HPTWWriteAdr;
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logic SetDirty;
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logic Dirty, Accessed;
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logic SetDirty;
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logic Dirty, Accessed;
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logic [P.XLEN-1:0] AccessedPTE;
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assign AccessedPTE = {PTE[P.XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]}; // set accessed bit, conditionally set dirty bit
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@ -194,8 +194,8 @@ module hptw import cvw::*; #(parameter cvw_t P) (
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end
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// Enable and select signals based on states
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assign StartWalk = (WalkerState == IDLE) & TLBMiss;
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assign HPTWRW[1] = (WalkerState == L3_RD) | (WalkerState == L2_RD) | (WalkerState == L1_RD) | (WalkerState == L0_RD);
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assign StartWalk = (WalkerState == IDLE) & TLBMiss;
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assign HPTWRW[1] = (WalkerState == L3_RD) | (WalkerState == L2_RD) | (WalkerState == L1_RD) | (WalkerState == L0_RD);
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assign DTLBWriteM = (WalkerState == LEAF & ~HPTWUpdateDA) & DTLBWalk;
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assign ITLBWriteF = (WalkerState == LEAF & ~HPTWUpdateDA) & ~DTLBWalk;
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@ -310,7 +310,7 @@ module hptw import cvw::*; #(parameter cvw_t P) (
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// multiplex the outputs to LSU
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if(P.XLEN == 64) assign HPTWAdrExt = {{(P.XLEN+2-P.PA_BITS){1'b0}}, HPTWAdr}; // extend to 66 bits
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else assign HPTWAdrExt = HPTWAdr;
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else assign HPTWAdrExt = HPTWAdr;
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mux2 #(2) rwmux(MemRWM, HPTWRW, SelHPTW, PreLSURWM);
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mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LSUFunct3M);
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mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M);
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