18 Commits

Author	SHA1	Message	Date
Ross Thompson	fc2b4453ec	rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory.	2022-03-29 23:48:19 -05:00
Ross Thompson	58668812c1	Moved WriteDataM register into LSU.	2022-03-23 14:17:59 -05:00
Ross Thompson	f1787670d4	Cleanup in testbench-linux.sv.	2022-03-22 22:34:38 -05:00
Ross Thompson	7fc128ba7c	added SIP, SIE, and SSTATUS to checkpoints. Can't seem to get the linux testbench to force SIP.	2022-03-22 21:28:34 -05:00
Ross Thompson	80d376877a	Added spoof of uart addresses +0x2 and +0x6.	2022-03-22 16:52:27 -05:00
bbracker	51e68819c4	fix up PLIC and UART checkpointing	2022-03-07 23:48:47 -08:00
bbracker	c2ac18b5de	change testbench-linux.sv to use new shared location of disassembly files	2022-03-07 20:04:08 -08:00
bbracker	5f5cc514b8	fix buildroot checkpointing and add it back to regression	2022-03-02 16:00:19 +00:00
bbracker	04ace8c154	switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv	2022-03-01 03:11:43 +00:00
David Harris	c12407ba6a	Removed Busybear dependencies	2022-02-02 20:28:21 +00:00
Ross Thompson	c1311ca56a	Fixed modelsim warning with linux simulation.	2022-01-31 12:57:02 -06:00
David Harris	2d112698b7	Replaced || and && with | and &	2022-01-31 01:07:35 +00:00
David Harris	ca1f7ce5d3	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
David Harris	2df92af488	Capitalized LSU and IFU, changed MulDiv to MDU	2022-01-07 04:30:00 +00:00
Ross Thompson	e74e8c2e86	Changed names of address in caches. ... Removed old cache files.	2022-01-05 22:19:36 -06:00
David Harris	d17a305538	Finished removing generate statements	2022-01-05 16:41:17 +00:00
David Harris	6d4714651c	Removed more generate statements	2022-01-05 16:25:08 +00:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00