naichewa
fbeaad4150
fifo fixes and edge case testing
2023-11-07 17:59:46 -08:00
David Harris
45e5e694ec
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-11-03 16:04:10 -07:00
naichewa
75658d5f8b
Merge branch 'main' into spi
2023-11-03 13:15:15 -07:00
David Harris
5e84d5e613
set default USE_SRAM=0 in memories; cleaned up synthesis script grep for cvw_t
2023-11-03 06:37:05 -07:00
David Harris
31adea3db0
Modified rams to take USE_SRAM rather than P to facilitate synthesis
2023-11-03 05:44:13 -07:00
David Harris
0b35c2ea56
Updated testbenches to capture InstrM because it may be optimized out of IFU
2023-11-03 05:24:15 -07:00
David Harris
9b7f385c50
Temporary fix of InstrM to prevent testbench hanging
2023-11-03 04:59:44 -07:00
David Harris
409ecc53bd
Fixed regression error of watchdog timeout when PCM is optimized out of the IFU
2023-11-03 04:38:27 -07:00
naichewa
08cf75783e
added test cases
2023-11-02 15:42:28 -07:00
naichewa
b59abc2dcc
correct exclusion tags and reset testbench
2023-11-01 10:34:39 -07:00
naichewa
8027a71e86
harris code review 3
2023-11-01 10:14:15 -07:00
David Harris
c639f92d27
Improved comments about memory read paths
2023-11-01 07:00:17 -07:00
naichewa
755c055f74
comments, more test cases
2023-11-01 01:26:34 -07:00
naichewa
792ddec064
code review harris
2023-10-31 12:27:41 -07:00
David Harris
d2ccba9a49
Conditionally instantiate hardware in ifu
2023-10-30 20:55:00 -07:00
David Harris
d0735887de
Gated InstrOrigM and PCMReg when not needed
2023-10-30 20:05:37 -07:00
David Harris
4bd830e578
rom1p1r code cleanup
2023-10-30 19:47:49 -07:00
David Harris
7b3dcdc262
rom1p1r code cleanup
2023-10-30 19:46:38 -07:00
David Harris
c472f4dc3c
Made 2-bit AdrReg conditional on being needed
2023-10-30 19:13:43 -07:00
naichewa
3570468ef5
Merge branch 'main' into spi
2023-10-30 17:01:41 -07:00
naichewa
7a0fb9a193
hardware interlock
2023-10-30 17:00:20 -07:00
David Harris
4d191e63cc
Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.
2023-10-30 09:56:17 -07:00
David Harris
12d1aed8a9
Fix issue 444 by preventing delegation of misaligned instructions when compressed instructions are supported.
2023-10-30 07:06:34 -07:00
David Harris
d5d196b870
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-10-26 19:02:05 -07:00
Rose Thompson
9ca3bfc2c8
Updated comments about Interrupt and wfi.
2023-10-26 12:24:36 -05:00
Rose Thompson
63bcc7655c
Forgot to include this file in the last commit.
2023-10-26 12:20:42 -05:00
Rose Thompson
dd9059317f
Cleaned up the implementation changes for wfi.
2023-10-24 23:11:48 -05:00
Rose Thompson
e4aebbaaa5
This version passes the regression test and solves issue #200 . wfi's implemenation is changed so that wfi does not take an interrupt in the Memory stage. Instead it advances to the Writeback stage then traps.
2023-10-24 22:58:26 -05:00
Rose Thompson
bc877e9ca7
Possible fix for wfi.
2023-10-24 18:08:33 -05:00
David Harris
17fd0c90da
Fixed warnings of signed conversion and for Design Compiler
2023-10-24 14:01:43 -07:00
Rose Thompson
bce15ce367
Added support for branch counters when there is no branch predictor.
2023-10-23 15:32:03 -05:00
Rose Thompson
2b031ea445
Fixed issue 250. instruction classification was not correct for jalr ra (non zero).
2023-10-23 15:30:43 -05:00
David Harris
aa3bc10259
Modified log2 coding to avoid synthesis warning
2023-10-19 11:16:02 -07:00
David Harris
09b3a49471
Removed unnecessary RV64 PWDATA muxing from AHB peripherals because LSU already replicates
2023-10-18 05:50:41 -07:00
naichewa
19e45a9182
Merge branch 'main' into spi
2023-10-16 22:59:50 -07:00
naichewa
95daef38d1
sync fifo passes
2023-10-16 22:57:02 -07:00
David Harris
b39ba7b4f8
Renamed wally-config to config in many comments
2023-10-16 13:49:09 -07:00
David Harris
b8a17afd5d
minfo test working again with mconfigptr for RV64
2023-10-15 06:41:52 -07:00
naichewa
59afc3b92c
always working after reg bit swizzle changes
2023-10-13 14:22:32 -07:00
naichewa
1fa4ad90ec
transferred spi changes in ECA-authorized commit
2023-10-12 13:36:57 -07:00
Ross Thompson
4a61d1b4f1
Fixed issue #412
...
The root cause was DTLB miss leads to page fault exception with concurrent I$ miss. The HPTW hits all entries in the D$ and quickly faults. However the I$ is still waiting on the main memory.
The trap then interrupts the atomimicity of the bus fetch and breaks the next several instructions.
The simplest solution is to use CommittedF to delay Exceptions like with Interrupts. Note this cannot happen with CommittedM. If the ITLB misses and the D$ also need to fetch a from the bus an ITLB page fault exception will not trigger the trap until a few stages later.
2023-10-09 16:03:37 -05:00
David Harris
d80cb36778
Added ZCA/ZCF/ZCD/ZCB support. Doesn't break regression, but not tested. Need to get tests for Zcb. Draft tests are in riscv-arch-test but not yet committed there
2023-10-04 12:28:12 -07:00
David Harris
42157eaf94
UpdateDA cleanup: don't assert UpdateDA when there is no SVADU
2023-10-04 09:57:13 -07:00
David Harris
df7f2679d7
Added MENVCFG.HADE bit and updated SVADU to depend on this bit
2023-10-04 09:34:28 -07:00
Ross Thompson
1a003019d6
Actually fixed non-power of 2 issue with RAS.
...
Added RAS swapping to branch predictor scripts and configurations.
2023-09-27 12:25:05 -05:00
Ross Thompson
9ec2bfd052
Fixed sutble RAS bug when the stack size was not a power of 2.
2023-09-27 12:00:47 -05:00
Ross Thompson
a910425adf
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-09-14 10:16:54 -05:00
Ross Thompson
7c89154a7f
Slight modification to cachefsm.
2023-09-05 14:07:58 -05:00
Ross Thompson
f00df8d121
Merge pull request #407 from davidharrishmc/dev
...
initial spill logic improvement
2023-09-05 13:29:37 -05:00
Ross Thompson
e39fc44efd
Merge pull request #406 from magpyed/cachesim_fix
...
Properly gate LRUWriteEn with ~FlushStage
2023-09-05 11:10:58 -05:00
