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Author SHA1 Message Date
David Harris
269bb688ea Fixed comment typo 2023-07-04 11:34:58 -07:00
David Harris
b04763bcf2 Commented SVADU requirements for wally32priv mmu tests 2023-07-04 11:34:07 -07:00
David Harris
410ef01627 fixed spacing in fdivsqrt 2023-07-04 11:27:36 -07:00
David Harris
001d3cfdc5 Added logic to warn about x in memory reads. Added cbo instruction names to testbench decoder 2023-07-02 13:29:27 -07:00
David Harris
afe66d0ee4 Added prefetch instructions; sent cbo instructions to LSU 2023-07-02 10:55:35 -07:00
David Harris
723b8266cb Added prefetch signals 2023-07-02 10:06:58 -07:00
David Harris
482e4e6e92 Enhanced decoder to produce individual CMOpE output for the 4 CMO instructions 2023-07-02 09:35:05 -07:00
David Harris
c48283801a Fixed csr typos 2023-07-02 02:01:40 -07:00
David Harris
61208e486c Fixed ENVCFG to reply on both MENVCFG and SENVCFG when in user mode 2023-07-02 02:00:27 -07:00
David Harris
b6ae5661b4 Added environment configuration control (menvcfg/senvcfg) of cbo instructions 2023-07-02 01:52:25 -07:00
David Harris
15314a9c9a Gated floating-point load/stores with STATUS_FS and added initial decoding for Cache Management Operations 2023-07-02 00:34:30 -07:00
David Harris
41e9f20943 improved decoder checking atomic and RW and MW and privileged instructions 2023-07-02 00:02:03 -07:00
David Harris
e34ef4d636 improved decoder checking atomic instructions 2023-07-01 23:10:57 -07:00
David Harris
d930be332e Improved instruction decoding for illegal floating-point loads/stores and fences 2023-07-01 22:48:04 -07:00
Ross Thompson
a8cdcaa26b Merge pull request #352 from stineje/main 
Change to testbench-fp.sv
 2023-06-29 11:30:01 -04:00
James E. Stine
67fdeae9c9 Add reset to wave window 2023-06-29 08:47:16 -05:00
James E. Stine
48bec40902 Modification (temporary) to testbench-fp.sv to allow testing of anything FMA. This might need to be changed with OpCtrl to make more robust for future expansion. 2023-06-29 08:46:11 -05:00
Ross Thompson
c6a55c446a Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-27 11:04:27 -05:00
Ross Thompson
cc5d8fbf06 Updates for fpga. 2023-06-27 11:04:20 -05:00
Ross Thompson
b1203b5460 Merge pull request #350 from stineje/main 
Minor tweak to fix vectors not working for fadd.
 2023-06-26 16:41:01 -04:00
James E. Stine
3cfec29cc7 Minor tweak to fix vectors not working for fadd. 2023-06-26 14:25:44 -05:00
Ross Thompson
1a936882f8 Merge pull request #349 from stineje/main 
Modification to testbench-fp.sv
 2023-06-26 12:51:57 -04:00
James E. Stine
dd6b12c6dc Add signals for ResMatch & CheckNow to sim window that are related to TestFloat operation 2023-06-26 10:15:46 -05:00
James E. Stine
786329b11d Fix items related to testing of TestFloat that were not always matching. The issue resulted due to the repeat statement that interferes with the always block. I separated the two to allow them to work correctly 2023-06-26 10:14:49 -05:00
David Harris
717c22a5d1 Merge pull request #348 from stineje/main 
Modify testfloat-fp.sv for parameterization
 2023-06-22 13:33:29 -07:00
James E. Stine
97b1c01dc0 Modify testbench-fp.sv to handle parameterization as well some other minor mods. Have to make a better FPUActive desgination but for now works 2023-06-22 15:27:17 -05:00
James E. Stine
0b7b28c2f0 For some reason this was modified - I probably made a mistake - put back vsim 2023-06-22 15:26:22 -05:00
James E. Stine
1f63e6d483 Remove path for cvw.sv so its found 2023-06-22 15:25:56 -05:00
Ross Thompson
7aecd72c35 Fpga does not correctly boot linux. I think the solution here is to revert out all substantive changes except for parameterization and then add them back in one at a time. This is necessary because the parameterization is not completed in one contiguous group of commits. 2023-06-22 12:55:49 -05:00
Ross Thompson
7550fd4bd9 Merge pull request #347 from kipmacsaigoren/unified_f_int_gen_fix 
fixed bug in combined intdivrem testvector extract script
 2023-06-22 12:38:45 -04:00
Kevin Kim
f6a3474550 fixed bug in testvector extract script 
-old script skips first 2 lines in rv32m case, new script only skips first line
- prior code skipped every other line in the reference file, so it only generated half the test vectors, with half of them having the wrong answer
- prior code also opened test vector file to be written to in "append" mode, and I changed to write mode (so that the script overwrites instead of adding to an existing file)
 2023-06-22 09:13:22 -07:00
Ross Thompson
0c924b0cac Merge pull request #346 from VictorClements/main 
FreeRTOS kernel submodule addin
 2023-06-21 18:26:42 -04:00
Victor Clements
1dfb2ae9e9 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-06-21 09:02:02 -07:00
Ross Thompson
55a0ccbbc9 Merge pull request #345 from stineje/main 
Update sim-testfloat to fix errors due to bad config element.  I am n…
 2023-06-20 18:29:24 -04:00
James E. Stine
66643eb78e Update sim-testfloat to fix errors due to bad config element. I am not sure of the reasoning, but the specific path to the testvector was not getting inserted in Questa. This modification also adds features to test individualized tests (.e.g, binary16 only) -- documentation is added in the FPbuild.txt file 2023-06-20 17:26:54 -05:00
Ross Thompson
a8f11dcad0 FPGA updates. 2023-06-20 11:11:34 -05:00
Ross Thompson
af187d96ca Updated fpga wave config. 2023-06-19 12:28:30 -05:00
Ross Thompson
1a23f1360f Updated fpga wally wrapper to work with the ILA. 2023-06-19 12:15:48 -05:00
Ross Thompson
f5cee3fb66 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-18 16:37:19 -05:00
Ross Thompson
cde2b1f2d2 Merge pull request #344 from davidharrishmc/dev 
Embench and coverage fixes
 2023-06-18 17:36:37 -04:00
David Harris
5d6eb40c2d Fixed embench to run all tests, even ones not in 1.0 2023-06-17 20:38:51 -07:00
harshinisrinath
f9d3944cc5 Improved testing of pmd in priv. 2023-06-16 17:13:54 -07:00
David Harris
46b83ad6a4 Merge pull request #343 from harshinisrinath1001/main 
Improve test coverage on ieu fw.
 2023-06-16 16:11:51 -07:00
harshinisrinath
d018357914 Improve test coverage on ieu fw. 2023-06-16 16:09:48 -07:00
David Harris
2db94e7ddd Replaced zext.h with zext.h_64 in rv64 tests because old one is obsolete 2023-06-16 16:07:28 -07:00
David Harris
c383407d5c Removed redundant and not-covered atomic check from StoreStallD 2023-06-16 16:05:53 -07:00
Ross Thompson
0423d7df82 I think the fpga is building again, but the debugger script needs to be updated. For some reason the nets are not present despite being marked debug. 2023-06-16 17:00:27 -05:00
Ross Thompson
443c568994 Vivado requires an intermediate wrapper file for parameterization. 2023-06-16 16:30:14 -05:00
Ross Thompson
c44d4321fb FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization. 2023-06-16 15:40:13 -05:00
David Harris
b1bfba7995 erge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-06-16 10:32:37 -07:00