Ross Thompson
f6393d1288
Waiting on fix for wally64periph uart test.
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would like to remove vectored interrupt adder.
2022-12-21 13:16:09 -06:00
Ross Thompson
c41d58bd29
Vectored interrupts now require 64 byte alignment.
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Eliminates adder.
2022-12-21 12:05:49 -06:00
Ross Thompson
2b1e9f8bed
The optimzied PC+2/4 logic still hanges on wally32priv.
2022-12-21 09:19:34 -06:00
Ross Thompson
a2329c8e9d
Renamed PCPlusUpperF to PCPlus4F.
2022-12-21 09:18:30 -06:00
Ross Thompson
a6ffb4cef3
Added timeout check to testbench.
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A watchdog checks the value of PCW. If it does not change within 1M cycles immediately stop simulation and report an error.
2022-12-21 09:18:00 -06:00
Ross Thompson
3fc121ef70
Fixed minor bug in PLIC. reading interrupt source 0 should not return x. it should provide produce 0.
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Switched to even simplier PC+2/4 logic.
2022-12-21 09:00:09 -06:00
Ross Thompson
968e174d68
Changes to wave file.
2022-12-21 08:41:47 -06:00
Ross Thompson
bc5d5e902a
Comments about PC+2/4.
2022-12-21 08:35:43 -06:00
David Harris
28085ce8eb
Clean up vecgtored interrupts
2022-12-20 16:53:09 -08:00
David Harris
88ee834c97
Converted tvecmux to structural
2022-12-20 16:24:04 -08:00
Ross Thompson
6152c028db
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-20 18:09:37 -06:00
Ross Thompson
2f0d20b8b0
privileged pc mux cleanup.
2022-12-20 18:05:44 -06:00
Ross Thompson
cba2ed64e5
Moved privileged pc logic into privileged unit.
2022-12-20 17:55:45 -06:00
David Harris
07dc11a508
IFU mux for CSRWriteFenceM conditional on ZICSR/ZIFENCEI
2022-12-20 15:38:30 -08:00
Ross Thompson
b4bdf446cc
Implement FENCE.I as NOP when ZIFENCEI is not supported.
2022-12-20 17:34:11 -06:00
Ross Thompson
d9a1870a31
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-20 17:11:35 -06:00
Ross Thompson
ef4ecbe62b
Changed long names of vectored pcm signals.
2022-12-20 17:01:20 -06:00
David Harris
f03d4e6b5a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-12-20 14:43:33 -08:00
David Harris
9133b3a7a4
FPU remove unused signals
2022-12-20 14:43:30 -08:00
Ross Thompson
be1bbf486e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-20 16:36:44 -06:00
Ross Thompson
637df763ca
Renumbered bits for PCPlusUpper.
2022-12-20 16:33:49 -06:00
David Harris
4c4b8db498
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-12-20 11:23:53 -08:00
David Harris
8f0ef29349
Memory cleanup
2022-12-20 11:22:26 -08:00
Ross Thompson
ca6076445b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-20 12:58:59 -06:00
Ross Thompson
d35fc5e2a6
Reorganized IFU PCNextF logic.
2022-12-20 12:58:54 -06:00
David Harris
c26c3b76ea
Renamed renamed sram to ram
2022-12-20 08:36:45 -08:00
David Harris
1ec62606f9
sram1p1rw cleanup
2022-12-20 02:57:51 -08:00
David Harris
0883736c88
Remoed unused bram modules
2022-12-20 02:40:45 -08:00
David Harris
9ad5552e89
Renamed SRAM2P1R1W to lower case
2022-12-20 02:09:55 -08:00
David Harris
b575f6242e
Renamed SRAM2P1R1W to lower case
2022-12-20 02:09:36 -08:00
David Harris
0c10ec942a
Replaced || and && with single ops
2022-12-20 01:33:35 -08:00
Ross Thompson
67e0b021ae
several options for pcnextf on fence.i
2022-12-19 23:33:12 -06:00
Ross Thompson
d18ef45c18
More bp/ifu pcmux cleanup.
2022-12-19 23:16:58 -06:00
Ross Thompson
761cf54dcc
Moved more muxes inside bp.
2022-12-19 22:51:55 -06:00
Ross Thompson
0097c166d6
Begin cleanup of ifu. partial move of pc muxes inside bp.
2022-12-19 22:46:11 -06:00
David Harris
954051da13
Removed CSR support from rv32i
2022-12-19 16:15:12 -08:00
David Harris
2393915bf2
Simplified InstrRawD register
2022-12-19 15:18:42 -08:00
David Harris
aac4b55b59
Explained hazard causes
2022-12-19 09:41:41 -08:00
David Harris
16b8fbbd2d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-12-19 09:09:57 -08:00
David Harris
b5958b1e11
Properly decode fcvtint to prevent unnecessary stalls
2022-12-19 09:09:48 -08:00
Ross Thompson
ddde82f928
Renamed FStallD to FPUStallD.
2022-12-19 09:28:45 -06:00
Alessandro Maiuolo
13c9f2e4a5
Added NumZeroE, AZeroM, and BZeroM
2022-12-18 20:02:40 -08:00
Alessandro Maiuolo
3bcb42adb6
fixed LOGRK. FIxed Xs in WC and WS from muxes reliant on SqrtE. note not linting on 4 copies radix 4 because IntBits only 7 bits wide (need 8)
2022-12-18 19:04:36 -08:00
Ross Thompson
c3b77926d5
I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl.
2022-12-18 18:30:35 -06:00
Ross Thompson
7a352edf13
Attempted to make a cache test.
2022-12-18 17:15:08 -06:00
Ross Thompson
9d1cb9337e
Updated tests for fpga and BP.
2022-12-18 16:24:26 -06:00
Ross Thompson
5acdf541b9
Finally fixed the lru bug. It was actually a flush bug all along. At the end of flush writeback FlushAdr is incremented so clearly the dirty bit then clears the wrong set. Must either take an additional cycle to clear dirty and then change the address or clear the dirty bit before the cache bus acknowledgment. Changed it to clear at begining of that line's writeback before actually writting back.
2022-12-17 23:47:49 -06:00
Ross Thompson
9849983348
At long last found the subtle bug in the LRU.
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Since the LRU memory is two ports, 1 read and 1 write, a write in cycle 1 to address x should not
forward data to a read from address y in cycle 2.
A read form address x in cycle 2 would still require forwarding.
2022-12-17 10:03:08 -06:00
Ross Thompson
c985988867
Fixed a bug with the new cache flush changes.
2022-12-16 19:28:32 -06:00
Ross Thompson
9b9e954cc5
Cleanup comments.
2022-12-16 17:08:35 -06:00
