13 Commits

Author	SHA1	Message	Date
Brett Mathis	11e2666bb2	Parallel FSR's and F CTRL logic	2021-02-04 02:25:55 -06:00
Noah Boorstin	cca60ed06d	update busybear testbench to conform to new structure ... aaaaaaaaaaaaaaaaaahhhh so many changes also the testbench now uses another internal signal, which I don't like, but I can't think of a better option rn	2021-01-30 19:19:00 +00:00
David Harris	9511dcac84	Connected AHB bus to Uncore	2021-01-29 23:43:48 -05:00
David Harris	9530039e3d	Implemented adrdec for uncore	2021-01-29 17:28:53 -05:00
Teo Ene	f0bbd71874	Added AHBW to rv32ic config file as well	2021-01-29 12:29:08 -06:00
Noah Boorstin	7183910c84	update busybear testbench to conform to new structure	2021-01-29 17:46:50 +00:00
David Harris	4687d6998a	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-01-29 01:07:22 -05:00
David Harris	e4e95bf941	Added ahblite bus interface unit	2021-01-29 01:07:17 -05:00
Noah Boorstin	0fa7cffb11	busybear: lie about MISA to match OVP's MISA	2021-01-29 00:58:56 -05:00
David Harris	4318629b32	Repartitioned datapath and controller into ieu	2021-01-27 06:40:26 -05:00
Noah Boorstin	91dcffa26f	Update busybear tests to conform to new directory structure	2021-01-25 20:37:18 -05:00
David Harris	b7988e536f	Reset Vector moved to config file	2021-01-25 15:57:36 -05:00
David Harris	bf07ec92b5	Added test configurations	2021-01-25 11:28:43 -05:00