Github_Repos/cvw
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9,221 Commits 5 Branches 2 Tags 53 MiB
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324 Commits

Author SHA1 Message Date
David Harris
bc70f0b933
Merge pull request #869 from jordancarlin/installation 
Installation and setup overhaul
 2024-08-08 15:39:23 -07:00
Jacob Pease
8c96c06022 Commented out rvvi debug probes in wally.tcl. 2024-08-08 13:52:53 -05:00
Jacob Pease
ed0c826d74 Turned off RVVI by default. 2024-08-08 13:50:11 -05:00
Jordan Carlin
76eef03fe4
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation 2024-08-07 20:22:55 -07:00
Jacob Pease
2dc7e0f76f Added and extra header and changed the comments to be accurate in ram1p1rwbe.sv 2024-08-06 17:36:42 -05:00
Jacob Pease
280b5baa59 Added header to new bootloader files. 2024-08-06 17:28:50 -05:00
Jacob Pease
954e21148f Removed line referring to local file in wally.tcl. 2024-08-06 17:11:08 -05:00
Jacob Pease
af2344d2d5 Merge branch 'main' of github.com:openhwgroup/cvw into spiboot 2024-08-06 17:09:39 -05:00
Jacob Pease
665396fdb3 SD card is now mountable on the fpga. The relevant files have been added. The most important changes are in the buildroot linux configuration and device tree. 2024-08-06 16:57:57 -05:00
Jacob Pease
ad9c98c19c Added file necessary to split boot.mem into boot.mem and data.mem. 2024-08-02 15:36:06 -05:00
Jacob Pease
83b0a83d5c Removed HSELEXTSDC and fixed SD card pin definitions. 2024-08-02 15:35:18 -05:00
Jacob Pease
11a057b0b3 Updated wally source files for zsbl testing. 2024-08-02 15:33:57 -05:00
Jacob Pease
897f6561cd New bootloader now works. Added special print functions and print messages. sdclk is set to 3MHz after initialization currently. 2024-08-02 15:19:52 -05:00
Jacob Pease
fcd88d6e6f Added functions to read registers and print information on failure. Also added a getTime function for a pretty boot display. 2024-08-02 15:14:30 -05:00
Jacob Pease
38071d8267 Updated formatting of gpt.c and boot.c. 2024-07-31 11:12:05 -05:00
Jacob Pease
ee980e39f3 Added function to set SPI clock speed. 2024-07-31 11:00:44 -05:00
Jacob Pease
c4ae17c679 Cleaned up code formatting a bit and added ability to set the SD card clock speed. 2024-07-31 10:59:41 -05:00
Jacob Pease
a263f836f2 Added extra UART macros and functions for code readability and the ability to print decimal numbers. 2024-07-31 10:58:15 -05:00
Jordan Carlin
e851812608
Replace /opt/riscv after merge 2024-07-25 21:33:31 -07:00
Jordan Carlin
42a9bbf28d
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation 2024-07-25 21:21:57 -07:00
Jacob Pease
3975f60299 Added carriage returns to line feed characters. UART messages print properly now. 2024-07-25 13:05:57 -05:00
Jacob Pease
a36e846b02 Changed formatting and added new UART divsor calculation from OpenSBI. 2024-07-25 13:04:27 -05:00
Jacob Pease
336a413f31 Added ability to split boot.memfile into boot.mem and data.mem. 2024-07-25 11:19:15 -05:00
Jacob Pease
0dae881a0d Fixed SDCCLK name discrepency. 2024-07-24 22:48:31 -05:00
Jacob Pease
ebdf25a53b Commented out references to old axi IP from wally.tcl. 2024-07-24 22:47:15 -05:00
Jacob Pease
2caf9e93be Removed old axi IP from fpga Makefile. Added sed for data.mem file loaded into uncore ram. 2024-07-24 22:46:24 -05:00
Jacob Pease
d15be492cb Masked lower byte when writing to DLL. 2024-07-24 22:44:27 -05:00
Jacob Pease
286d80de7e Initialized UART with Arty frequency and baud rate. Will make this dynamic in the future 2024-07-24 22:43:47 -05:00
Jacob Pease
0107a400d1 Added uart header to gpt.c. 2024-07-24 22:43:16 -05:00
Rose Thompson
5cae55561e Removed unused file. 2024-07-24 13:30:25 -05:00
Rose Thompson
d0a5b278b7 Factored out the rvvi testbench code into rvvitbwrapper. 2024-07-24 13:10:57 -05:00
Rose Thompson
b1a711ae0f Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim. 2024-07-24 12:47:50 -05:00
Jacob Pease
f1cc7dd5a3 Fixed verilog bugs. 2024-07-23 17:26:39 -05:00
Jacob Pease
dcb2edf888 Fixed syntax bugs. inline functions are now static and in the spi.h header. 2024-07-23 17:00:32 -05:00
Jacob Pease
5f0addd69a Initial pass on SPI based bootloader code finished. 2024-07-23 16:33:49 -05:00
Jacob Pease
a8b9e7776b Added some minor error checking to gpt.c. 2024-07-23 16:32:52 -05:00
Jacob Pease
ab00ea5a5c Added sd_read64 to help with block reads and crc checking. 2024-07-23 16:32:29 -05:00
Jacob Pease
57eeba5c8c Progress made on implementing new disk read function. 2024-07-23 15:47:23 -05:00
Jacob Pease
9ccb0eb027 Removed references to card_type. 2024-07-23 15:46:18 -05:00
Jacob Pease
bf65cd2817 Added uart print functions and the Wally banner. SD card can now be initialized. Removed old code from boot.c 2024-07-23 14:18:42 -05:00
Rose Thompson
8ca565ed53 Updated for a better ILA rvvi debugger. 2024-07-22 17:44:04 -05:00
Jacob Pease
b05052311f Added sd_cmd and utility SPI functions. 2024-07-22 16:57:04 -05:00
Rose Thompson
121342f4cc Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI. 2024-07-22 16:12:06 -05:00
Jacob Pease
cec39fd3aa Added new SDC clock constraint. 2024-07-22 13:05:16 -05:00
Jacob Pease
a506d76149 Removed the old SDC. Added a second SPI peripheral that now will be used to control the SD card. SPI peripheral now outputs SPICLK. Removed references to the now non-existent external SDC in uncore. Removed all of the AXI Xilinx IP. 2024-07-22 12:36:39 -05:00
Rose Thompson
556c210e76 Added option to use rvvi ila 2024-07-22 12:19:37 -05:00
Rose Thompson
7223b15134 Merge branch 'rvvi' 2024-07-22 12:01:01 -05:00
Rose Thompson
24609f0b7f Now have configurations to switch between supporting RVVI over ethernet. 2024-07-22 10:51:13 -05:00
Jacob Pease
e91d2c8b14 Corrected the CRC7 code with the right sequence of instructions. 2024-07-22 01:19:10 -05:00
Jacob Pease
c7d869bc96 Added inital spi based sd card code. Working on CRC7 code that works. 2024-07-20 14:00:43 -05:00