99 Commits

Author	SHA1	Message	Date
David Harris	f38bb5b32e	Divide testfloat starts with half-precision tests	2022-09-18 06:46:47 -07:00
David Harris	19e449b83d	Fixed regression for divsqrt radix2	2022-09-07 06:12:23 -07:00
David Harris	09456db445	Checking in radix 4 square root with qsel, fgen, softc, but not working	2022-08-31 10:54:50 -07:00
David Harris	e1760dde55	Fixed checking termination in testfloat testbench	2022-08-30 10:55:21 -07:00
David Harris	4aa30c48aa	fixed wally-config	2022-08-26 22:13:10 -07:00
David Harris	37f0b52520	Fixed address decoder hanging buildroot	2022-08-26 22:01:25 -07:00
David Harris	d0dbc74492	Fixed DTIM/IROM_BASE number of bits in buildroot/fpga configs	2022-08-26 21:29:26 -07:00
David Harris	2b241f8bbd	Set bit width of DMEM/IROM_SUPPORTED and fixed address decoding	2022-08-26 21:18:18 -07:00
David Harris	03e731b3ff	Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM	2022-08-26 21:05:20 -07:00
David Harris	f0b4f69b65	Added IROM and DTIM decoding to adrdecs	2022-08-26 20:45:43 -07:00
David Harris	812158aeee	Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each	2022-08-26 20:26:12 -07:00
David Harris	95dd50a567	Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem	2022-08-26 20:12:03 -07:00
Ross Thompson	3b612d6201	Possible fixes for earily messup of rv32ic and rv64ic configs.	2022-08-25 14:42:08 -05:00
Ross Thompson	e605ef57dc	BROKEN. Don't use this commit. ... Issue running cacheless with bus.	2022-08-25 11:02:46 -05:00
Ross Thompson	769af32f2a	Renamed RAM to UNCORE_RAM.	2022-08-24 18:09:07 -05:00
Ross Thompson	51adf6cba9	Modified the lsu/ifu memory configurations.	2022-08-24 12:35:15 -05:00
David Harris	e714b75888	LSU minor edits	2022-08-23 07:35:47 -07:00
Katherine Parry	36be692c0b	sqrt passes - lint warnings remain	2022-08-22 17:16:12 +00:00
Katherine Parry	cb0c1b7488	radix-2 1 copy passes testfloat	2022-08-06 22:54:05 +00:00
Katherine Parry	de6ae471bc	fixed fsw problem and removed 2 bit shift from shift correction	2022-08-03 22:16:51 +00:00
Ross Thompson	69d520a7eb	Removed replay from the config files.	2022-07-24 00:34:11 -05:00
Katherine Parry	b3d932cd61	divider sizes reworked to match book	2022-07-22 22:02:04 +00:00
Katherine Parry	fbe8bb2298	radix-4 division integrated into srt - not tested	2022-07-21 19:38:06 +00:00
Katherine Parry	5cb9c9f319	merged floating-point radix-2 divider with radix-4	2022-07-15 20:16:59 +00:00
cturek	cabd41a5a0	Six tests passing and a bunch of sizizing issues fixed	2022-07-14 19:38:27 +00:00
Katherine Parry	2fe8b6e34c	fixed error in divsqrt	2022-07-14 18:16:00 +00:00
cturek	0b91e7526f	DIVLEN and counter updated for sqrt computation and rounding	2022-07-13 22:42:39 +00:00
cturek	97a1548356	radix 4 files removed from srt and divlen modified for sqrt	2022-07-13 19:46:48 +00:00
Katherine Parry	3c1bea1104	removed warnings and took a mux out of the critical path	2022-07-12 18:32:17 -07:00
Katherine Parry	bea4ec078d	variable interations implemented in radix-4 divider	2022-07-11 18:30:21 -07:00
Katherine Parry	75a8cea4e4	srt divider merged into fpu	2022-07-07 16:01:33 -07:00
Katherine Parry	c581fba4aa	modified wally shared	2022-07-07 21:59:43 +00:00
David Harris	f2915129ab	Preliminary SRAM integration	2022-07-07 19:56:20 +00:00
Katherine Parry	8ac722f693	Renaming signals to match chapter	2022-07-03 12:26:22 -07:00
cturek	7249295f53	Updated radix 2 divider to work with integers and floats in new structure. Integers still might not work.	2022-06-27 23:55:21 +00:00
Katherine Parry	70a1bb8377	fixed commented out error and removed killprod from result selection	2022-06-25 01:42:23 +00:00
slmnemo	528869ef14	Removed references to initialization files	2022-06-23 16:50:27 -07:00
Katherine Parry	de71773d69	added radix-4 0/d handling	2022-06-23 22:36:19 +00:00
Katherine Parry	1612daa294	Testfloat running division - not passing	2022-06-23 00:07:34 +00:00
Katherine Parry	03d823f5d7	added fld in rv32 - needs testing	2022-06-20 22:53:13 +00:00
Katherine Parry	2a8c17170c	hopefully fixed lint error	2022-06-17 00:14:39 +00:00
Katherine Parry	5f7072bd96	postprocessing unit created and passing all tests	2022-06-13 22:47:51 +00:00
DTowersM	4e5d7ec3d6	changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability	2022-06-10 00:37:53 +00:00
Katherine Parry	eb93bd46d7	fma synth warnings and errors removed	2022-06-06 16:06:04 +00:00
Katherine Parry	019994c802	removed some debuging code accedentally pushed	2022-06-02 22:45:19 +00:00
Katherine Parry	39101fcbb3	added config rv64fpquad	2022-06-02 22:09:11 +00:00
Katherine Parry	c5bde75e30	added createallvectors	2022-06-02 21:56:05 +00:00
Katherine Parry	ccda4c771e	fpu paramaterized - except fdivsqrt	2022-06-02 19:50:28 +00:00
slmnemo	61f077f62c	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-06-02 02:52:03 +00:00
slmnemo	35caa03e46	Updated Linux testbench to use new force/unforce method for Branch predictor init and removed related .txt files	2022-06-02 02:51:51 +00:00