3744 Commits

This Branch

This Branch

All Branches

Author	SHA1	Message	Date
David Harris	c60bb68bff	Testgen working for Lab 2	2022-01-26 18:01:51 +00:00
David Harris	492c1a488e	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-26 17:21:09 +00:00
David Harris	f90e58ff34	New testgen.py	2022-01-26 17:21:02 +00:00
bbracker	ea92cc3af2	a different approach to QEMU: add Wally as a completely new machine	2022-01-26 15:02:24 +00:00
Ross Thompson	728e46a794	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-01-25 19:21:04 -06:00
Ross Thompson	db197b6491	Added pin location for reset on VCU118 board. Somehow this was missing and still worked.	2022-01-25 17:48:42 -06:00
David Harris	1e533cdf25	Removed and restored embench-iot	2022-01-25 22:12:28 +00:00
Ross Thompson	71eb1df492	Added comport.setup to remind how to configure com port for xilinx fpga. ... Added load-deadlock.tsm to trigger load operation deadlock.	2022-01-25 14:54:38 -06:00
David Harris	22c84dcd80	simpleram simplification	2022-01-25 19:46:13 +00:00
David Harris	8bf73d0eb3	simpleram simplification	2022-01-25 19:40:07 +00:00
David Harris	f07123ff0f	simpleram simplification	2022-01-25 18:26:31 +00:00
David Harris	7ac44cb3fc	simpleram address simplification	2022-01-25 18:17:33 +00:00
David Harris	5eb71a3bbe	simpleram address simplification	2022-01-25 18:00:50 +00:00
David Harris	d9888c91a6	simpleram clk and reset simplification	2022-01-25 17:34:15 +00:00
David Harris	5cb879129e	Start of IFU cleanup	2022-01-25 17:31:53 +00:00
David Harris	0660e5fe51	removed sum executable	2022-01-25 10:24:05 +00:00
David Harris	44c58cfa20	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-25 06:53:07 +00:00
David Harris	4c8c359894	More example Makefile cleanup	2022-01-25 06:53:03 +00:00
davidharrishmc	6fa63bf6d7	Update README.md	2022-01-24 15:47:42 -08:00
davidharrishmc	edff52c692	Update README.md	2022-01-24 15:46:24 -08:00
David Harris	96e9cd6ef1	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-24 23:21:16 +00:00
David Harris	26013a984b	Fixed sumtest reference output; added embench benchmark directory	2022-01-24 23:21:09 +00:00
kaveh Pezeshki	3314fb48c4	added qemu patches in tests/linux-testgen/qemu	2022-01-24 07:52:07 +00:00
Ross Thompson	4d4d9ac8cf	Added spill support back into the IROM IFU.	2022-01-21 15:50:54 -06:00
Ross Thompson	4ecc2d029a	Changed the IROM and DTIM memories to behave like edge-triggered srams.	2022-01-21 15:42:54 -06:00
David Harris	c2c7351b24	erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-21 00:12:18 +00:00
David Harris	0bb63e9ad1	Fixed path to riscvOVPsimPlus	2022-01-21 00:12:14 +00:00
Ross Thompson	ec44774c77	Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv	2022-01-20 16:39:54 -06:00
David Harris	d1162eeebf	fir.c	2022-01-20 17:15:53 +00:00
David Harris	ac28880cd9	Added FIR example	2022-01-20 16:57:36 +00:00
David Harris	ca1f7ce5d3	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
David Harris	0d0aa59e48	Removed imperas tests from makefile for now	2022-01-20 14:51:56 +00:00
David Harris	f420e63ed0	Added top-level make clean	2022-01-20 14:17:26 +00:00
David Harris	537cb1d1e1	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-20 00:04:27 +00:00
David Harris	ab25aa4df9	Created linux directory for linux config	2022-01-20 00:04:23 +00:00
Ross Thompson	05ebadacad	Added PCNextF and PostSpillInstrRawF to ila.	2022-01-19 14:05:14 -06:00
Ross Thompson	305fccfe7a	Fixed fpga ila debug to match lsu changes.	2022-01-18 21:13:18 -06:00
David Harris	f966d98e56	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-19 00:26:34 +00:00
Ross Thompson	5cf686429d	Merged in the debug ila updates.	2022-01-18 17:29:21 -06:00
Ross Thompson	2508b9d35a	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-01-18 17:19:59 -06:00
Ross Thompson	fdc17f5017	Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes.	2022-01-18 17:19:33 -06:00
David Harris	1a21e7f011	riscvsingle reparittioned to match Ch4	2022-01-17 16:57:32 +00:00
David Harris	de7b9c127e	Added E extension, and downloaded riscv-dv and embench-iot to addins	2022-01-17 14:42:59 +00:00
David Harris	5842d780a7	Defined rv32e and rv32emc configs	2022-01-17 14:01:01 +00:00
David Harris	8b62130070	lsu cleanup down to 346 lines	2022-01-15 01:19:44 +00:00
David Harris	b967bcede2	LSU Cleanup	2022-01-15 01:11:17 +00:00
David Harris	f7f3882cb8	Moved Dcache into bus block	2022-01-15 00:39:07 +00:00
David Harris	d9e8d16bbe	Renamed LSUStall to LSUStallM	2022-01-15 00:24:16 +00:00
David Harris	b0263012e8	LSU cleanup	2022-01-15 00:11:30 +00:00
David Harris	4c5962095e	LSU cleanup	2022-01-15 00:03:03 +00:00