14 Commits

Author	SHA1	Message	Date
David Harris	1206b388c7	Replaced dtim with rom-based IROM in IFU. Moved cache control signals out of DTIM and IROM	2022-08-25 04:06:27 -07:00
David Harris	f7209627c2	removed simpleram and modified dtim to use bram1p1rw	2022-08-25 03:39:57 -07:00
Ross Thompson	769af32f2a	Renamed RAM to UNCORE_RAM.	2022-08-24 18:09:07 -05:00
Ross Thompson	3b07584403	Updated the names of the *WriteDataM inside the LSU to more meaningful names. ... Moved the FWriteDataMux so that the bus and dtim both get fpu stores. Modified the PMA to disallow double sized reads when XLEN=32.	2022-08-23 10:34:39 -05:00
Ross Thompson	1993069986	Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.	2022-03-30 11:04:15 -05:00
Ross Thompson	d347de8c49	dtim writes are supressed on non cacheable operation.	2022-03-12 00:46:11 -06:00
Ross Thompson	3dbf6790e1	Towards allowing dtim + bus.	2022-03-11 14:58:21 -06:00
Ross Thompson	bdfca503fa	Name cleanup.	2022-03-10 18:44:50 -06:00
Ross Thompson	d77adbd673	Signal name cleanup.	2022-03-10 18:26:58 -06:00
Ross Thompson	50789f9ddd	Byte write enables are passing all configs now.	2022-03-10 17:26:32 -06:00
David Harris	096242a6d8	Merged TIM and regular testbenches. RV32e now working and back in regression.	2022-02-08 12:18:13 +00:00
Ross Thompson	a04aa283cb	partial ifu cleanup.	2022-01-31 16:08:53 -06:00
Ross Thompson	b05abc1795	cleanup.	2022-01-31 13:29:04 -06:00
Ross Thompson	e35a8299ec	Encapsulated dtim.	2022-01-31 11:23:55 -06:00