218 Commits

Author	SHA1	Message	Date
David Harris	f262abb5c3	Removed unused signals	2022-08-25 18:34:39 -07:00
David Harris	b73286ece6	Removed unused signals	2022-08-25 18:30:46 -07:00
David Harris	949e76bc83	Removed UncachedBusRead and UncachedBusWrite	2022-08-25 18:24:39 -07:00
David Harris	e39694694c	Restored ahbtranstype	2022-08-25 18:22:26 -07:00
David Harris	83d3782f2c	Removed ahbtranstype	2022-08-25 18:21:45 -07:00
David Harris	543fbd1fa9	Removed WordCountFlag	2022-08-25 18:21:18 -07:00
David Harris	d118fcbde8	Removed UncachedAccess	2022-08-25 18:20:52 -07:00
David Harris	bac95823b6	Removed UncachedRW	2022-08-25 18:19:41 -07:00
David Harris	cfcde754c3	Removed CacheBusAck	2022-08-25 18:17:34 -07:00
David Harris	9bc62ce124	Removed SelUncachedAdr	2022-08-25 18:15:59 -07:00
David Harris	f39e62eeea	Removed Cache_Enabled	2022-08-25 18:13:34 -07:00
David Harris	5bfaf31df0	Removed STATE_BUS_FETCH and STATE_BUS_WRITE	2022-08-25 18:12:09 -07:00
David Harris	85e93e2bb7	Removed CacheFetchLine and CacheWriteLine	2022-08-25 18:10:15 -07:00
David Harris	23a102b1b9	Removed CountEn	2022-08-25 18:05:44 -07:00
David Harris	e485e986a5	Removed wordcount	2022-08-25 18:04:49 -07:00
David Harris	69dff87feb	Added buscachefsm for system with bus and cache	2022-08-25 18:01:01 -07:00
David Harris	5340c45dfc	Separated busdp for cache from simpler logic for no cache	2022-08-25 17:54:04 -07:00
David Harris	9a92bfe095	Simplified swbytemask	2022-08-25 17:32:16 -07:00
David Harris	eb753b3b3f	FIxed wallypipelinedsoc merge conflict	2022-08-25 15:36:47 -07:00
David Harris	902d2067ba	Removed delayed AHB signals from top level	2022-08-25 15:34:14 -07:00
Ross Thompson	5c2bc20dbd	Almost fixed issues with irom and dtim address selection.	2022-08-25 15:52:25 -05:00
Ross Thompson	d23888407b	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-25 14:45:02 -05:00
David Harris	1226b2889e	ahblite cleanup	2022-08-25 12:44:25 -07:00
Ross Thompson	f67010c688	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-25 14:40:52 -05:00
David Harris	bc0c7d0cd8	Cleaned up SelBusWord	2022-08-25 11:18:13 -07:00
David Harris	c442dea173	Removed M sufix from busdp signals	2022-08-25 11:13:01 -07:00
David Harris	48f346baf8	Renamed LSUFunct3M to Funct3 in busdp	2022-08-25 11:08:12 -07:00
David Harris	9bada9c14a	Renaming LSU signals from busdp	2022-08-25 11:05:10 -07:00
David Harris	3ba961d1a8	renamed BusBuffer to FetchBuffer	2022-08-25 10:44:39 -07:00
David Harris	dda3b441d7	Continued busdp/ebu simplification	2022-08-25 10:20:02 -07:00
David Harris	aba914ea5e	Renamed AHB signals coming out of LSU to LSH_<AHBNAME>	2022-08-25 09:52:08 -07:00
Ross Thompson	e605ef57dc	BROKEN. Don't use this commit. ... Issue running cacheless with bus.	2022-08-25 11:02:46 -05:00
David Harris	ae0702d129	Renamed DCache to Cache in busdp/busfsm signal interface	2022-08-25 06:21:22 -07:00
David Harris	db5c941d6f	Minor name cleanups	2022-08-25 04:28:25 -07:00
David Harris	1206b388c7	Replaced dtim with rom-based IROM in IFU. Moved cache control signals out of DTIM and IROM	2022-08-25 04:06:27 -07:00
David Harris	f7209627c2	removed simpleram and modified dtim to use bram1p1rw	2022-08-25 03:39:57 -07:00
Ross Thompson	769af32f2a	Renamed RAM to UNCORE_RAM.	2022-08-24 18:09:07 -05:00
Ross Thompson	51adf6cba9	Modified the lsu/ifu memory configurations.	2022-08-24 12:35:15 -05:00
Ross Thompson	e4cbb43c67	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-23 18:52:15 -05:00
Ross Thompson	642dc170d7	Found small bug in busfsm which was issuing 1 extra memory read after each cache line fetch. Does not appear to have translated to an extra read out of ahblite.	2022-08-23 18:51:11 -05:00
David Harris	c61dba6192	Fixed LSU typos	2022-08-23 10:23:08 -07:00
Ross Thompson	aa5cbab0d8	Replaced LSU data replication with 0 extention.	2022-08-23 10:43:47 -05:00
Ross Thompson	3b07584403	Updated the names of the *WriteDataM inside the LSU to more meaningful names. ... Moved the FWriteDataMux so that the bus and dtim both get fpu stores. Modified the PMA to disallow double sized reads when XLEN=32.	2022-08-23 10:34:39 -05:00
David Harris	e714b75888	LSU minor edits	2022-08-23 07:35:47 -07:00
David Harris	3c91df95d9	Named HTRANS states in busfsm	2022-08-22 13:56:46 -07:00
David Harris	0e489443f2	Finished FPU-LSU interface cleanup	2022-08-22 13:43:04 -07:00
David Harris	8444eca57c	Simplified FPU-LSU interface to skip IEU	2022-08-22 13:29:20 -07:00
Ross Thompson	ebe4339953	Updated fpga test bench. ... Solved read delay cache bug. Introduced during cache optimizations.	2022-08-21 15:59:54 -05:00
Ross Thompson	2ba390adf4	Possible reduction of ignorerequest.	2022-08-19 18:07:44 -05:00
Ross Thompson	517c0f6c35	Changed signal names.	2022-08-17 16:12:04 -05:00