Harshini Srinath
ec0454111f
Update adrdecs.sv
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Program clean up
2023-06-12 18:22:32 -07:00
Harshini Srinath
b1ee6bfde5
Update adrdec.sv
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Program clean up
2023-06-12 17:28:21 -07:00
Ross Thompson
a963f0af3a
Updated source code to be compatible with verilator 5.011 for lint only.
2023-05-31 10:44:23 -05:00
Ross Thompson
8e1476cb8c
Possible fix for Linux bug and bug 203. ImperasDV mismatches in linux boot around 571M instructions after the login prompt.
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This bug occurs when there are back to back HPTW requests and the first generates an access fault during the walk. The old implementation uses a delayed version of the fault to prevent the HTPW fsm from transitioning out of the IDLE state. Because the first request generates the fault and the second request is pipelined the second request appears as if it also faults so the FSM does not perform the walk.
The new implementation adds a FAULT state. When the HPTW generates an access fault it transitions to this state removes the HPTWStall and then transitions to IDLE. There may still be a remaining bug here if the pipeline is stalled for another reason. However I don't think it is possible by construction. The only possible sources of stalls at this point would be IFU and LSU stalls and both are required to make this condition happen.
2023-05-30 15:20:24 -05:00
Ross Thompson
02a788a083
PMA checker's address decoder is now parameterized. I did not see bit slicing in Lim's code. I'm not sure how they got around this issue.
2023-05-26 11:06:48 -05:00
Ross Thompson
0020d94b39
Updated mmu's tlb and hptw to use Lim's parameterization.
2023-05-24 18:02:22 -05:00
Ross Thompson
70c8828ac2
PM(P/A) checkers parameterized based on Lim's work.
2023-05-24 17:20:55 -05:00
Ross Thompson
fcb1c63f5f
Partial parameterization into mmu.
2023-05-24 16:12:41 -05:00
David Harris
d5b718be38
IMMU exclude non word-sized accesses
2023-05-01 08:14:19 -07:00
David Harris
6253c042b2
Merged coverage exclusions for PMP
2023-04-28 08:04:25 -07:00
David Harris
194b848fbf
PMA Checker coverage
2023-04-28 07:53:59 -07:00
David Harris
af7959a3e2
Commenting
2023-04-28 07:52:08 -07:00
David Harris
9843223ddd
Removed clear from TLBLRU because there is no need to flush LRU state and it causes coverage issues
2023-04-28 07:03:46 -07:00
Liam
4d8eafd27d
Pmpadrdecs test cases changing AdrMode to 2 or 3
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Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] writing values to pmpcfg0 to change AdrMode to 2 or 3
Also exclusion for pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1 in pmpadrdec.sv
2023-04-27 12:23:35 -07:00
Limnanthes Serafini
034c289a36
Misc typo and indent fixing.
2023-04-13 16:54:15 -07:00
Ross Thompson
e531b0103e
Fixed wally64/32priv test hangup.
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The fix for the issue 203 had a lingering bug which did not suppress a bus access if the hptw short circuits on a pma/p fault.
2023-04-05 23:13:45 -05:00
Ross Thompson
394f2d65f2
Progress on bug 203.
2023-04-05 13:20:04 -05:00
David Harris
2e5c50e24a
Fixed RV32 tests after PMP fix
2023-03-28 08:35:23 -07:00
David Harris
e8904411ce
Fixed PMP issue 132. Updated tests to initialize PMP before using. Needs to remake tests
2023-03-28 06:58:17 -07:00
Ross Thompson
46b1bca4fc
Fixed all tap/space issue in RTL.
2023-03-24 17:32:25 -05:00
David Harris
a1eccf37dc
Fix Issue 145
2023-03-22 04:33:14 -07:00
David Harris
ff22520d9e
Added comments about PMP checker fixes when test cases will be ready to initialize PMP before entering user mode
2023-03-19 05:46:34 -07:00
Ross Thompson
e448cd54ef
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-03-06 18:39:15 -06:00
Ross Thompson
31fcc0daf7
Renamed PCFSpill to PCSpillF.
2023-03-06 17:50:57 -06:00
David Harris
23775c6d67
Renamed I/D TLBMissOrDAFault to TLBMissOrUpdateDA for consistency with UpdateDA
2023-03-01 11:18:00 -08:00
David Harris
f40352e82b
hptw typo fix
2023-02-26 19:38:34 -08:00
David Harris
e9ad6ae057
Simplified Access fault logic in HPTW
2023-02-26 18:50:37 -08:00
David Harris
2d7145901b
StoreAmo faults are generated instead of load faults on AMO operations
2023-02-26 18:35:10 -08:00
David Harris
21b28fd1bb
Renamed DAPageFault to UpdateDA
2023-02-26 17:51:45 -08:00
David Harris
4274071333
renamed UpperBitsUnequalPageFault to UpperBitsUnequal
2023-02-26 17:32:34 -08:00
David Harris
06bd4783af
moved tlb to subdirectory
2023-02-26 17:31:03 -08:00
David Harris
c774b44116
Moved TLB into subdirectory of MMU
2023-02-26 17:28:05 -08:00
David Harris
dc447ed5ed
Removed unneeded TLBFlush from TLBMiss
2023-02-26 10:04:16 -08:00
David Harris
54b8e7c629
Access faults are geted by ~TLBMiss rather than ~(Translate & ~TLBHit)
2023-02-26 09:58:34 -08:00
David Harris
35653a18b7
Renamed HPTW_WRITES_SUPPORTED to SVADU_SUPPORTED
2023-02-26 09:38:32 -08:00
David Harris
f31764c3e1
Renamed DAPageFault to HPTWDAPageFault in hptw to avoid name conflict with DAPageFault from tlbcontrol
2023-02-26 07:12:43 -08:00
David Harris
8895114152
Fixed SSTC being unusable in M-MODE without Status.TM. Disable STIMECMP registers when SSTC_SUPPORTED = 0
2023-02-26 06:30:43 -08:00
David Harris
adfc01fc5a
Fixed special cases of address decoder and documented better
2023-02-24 07:52:46 -08:00
David Harris
00d54cfe6c
PMP checker size check to avoid spurious warnings
2023-02-19 16:08:23 -08:00
David Harris
fa0406b554
Moved conditional instantiation outside pmpchecker
2023-02-19 15:31:00 -08:00
Ross Thompson
c33230d1c1
Fixed Bug 66.
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If a load missed at the same time as a spilled instruction fetch with an ITLB miss in the second cache line, the HPTW did not wait for the load miss to finish.
2023-02-06 17:32:28 -06:00
Ross Thompson
4e8ef4a0ac
Removed unreachable if branch in hptw next state logic.
2023-02-06 16:42:07 -06:00
David Harris
78eb90715c
Removed pipelined level of hierarchy
2023-02-02 14:14:11 -08:00
