bbracker
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d8ddda760b
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deprecate imperas64p tests and move them over to the privilege configuration of wally-riscv-arch-test
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2022-03-01 00:37:46 +00:00 |
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David Harris
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329fea9329
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Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath
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2022-02-28 20:50:51 +00:00 |
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bbracker
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ac114e1c6d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-02-22 04:27:50 +00:00 |
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bbracker
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202bd2f8f8
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change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests
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2022-02-22 03:46:08 +00:00 |
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Kip Macsai-Goren
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04892c5d38
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added scratch register tests for 64 and 32 bits
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2022-02-21 07:03:12 +00:00 |
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Kip Macsai-Goren
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324efa7d42
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added 32 bit pma tests to regression even though they've been working fo a while
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2022-02-18 19:43:24 +00:00 |
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Kip Macsai-Goren
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dcb5d0f6a9
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Added misa test for both 32 and 64 bits
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2022-02-18 19:41:50 +00:00 |
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Kip Macsai-Goren
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e16581d73d
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added CSR permission and minfor to 32 bit tests
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2022-02-15 20:19:14 +00:00 |
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Kip Macsai-Goren
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943c4d9d7c
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merged test macros in with 32 bit tests
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2022-02-15 20:19:14 +00:00 |
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David Harris
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f734afb866
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Just needed to recompile - all good. Now removed uretM because N-mode is depricated
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2022-02-15 19:48:49 +00:00 |
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Kip Macsai-Goren
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9ff4025844
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light cleanup for privileged tests
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2022-02-15 17:06:16 +00:00 |
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David Harris
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64e9f4c0d3
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Restored E tests to makefrag
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2022-02-08 16:41:11 +00:00 |
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David Harris
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f00b3ac27e
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Fixed TIM tests; rv32e test still failing
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2022-02-08 15:24:37 +00:00 |
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David Harris
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76dccbad91
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Patching up testbench; fixed false passing, but rv32ic and rv32e tests now fail
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2022-02-08 12:40:02 +00:00 |
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David Harris
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c61cd55c5c
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Merged TIM and regular testbenches. RV32e now working and back in regression.
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2022-02-08 12:18:13 +00:00 |
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David Harris
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cbef88ec10
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Lab 3 file cleanup
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2022-02-08 10:26:37 +00:00 |
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Kip Macsai-Goren
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0eb280b314
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added new tests to make and testbench
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2022-02-06 19:47:22 +00:00 |
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bbracker
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f67af23bf3
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remove sporadic tabs from tests.vh so that it is now only spaces
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2022-02-05 23:07:38 +00:00 |
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David Harris
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72bc64ef28
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Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.
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2022-02-05 04:16:18 +00:00 |
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David Harris
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2c67f32b97
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RV32e tests
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2022-02-04 14:30:36 +00:00 |
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David Harris
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a6708ed887
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cache cleanup
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2022-02-03 15:36:11 +00:00 |
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David Harris
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38bbe23d14
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More config file cleanup; 32ic tests broken
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2022-02-03 01:08:34 +00:00 |
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David Harris
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da8819d64b
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changed DMEM and IMEM configurations to support BUS/TIM/CACHE
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2022-02-03 00:41:09 +00:00 |
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David Harris
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02071700d6
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Removed Busybear dependencies
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2022-02-02 20:28:21 +00:00 |
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Ross Thompson
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f4a553fd7d
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Fixed testbench so coremark stops.
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2022-02-02 11:37:48 -06:00 |
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Ross Thompson
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4b4cee3ddd
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Added correct stop condition for coremark.
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2022-02-02 09:53:51 -06:00 |
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Ross Thompson
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143bdaa288
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Modified makefiles to generate function address to name mappings for modelsim.
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2022-02-01 18:25:03 -06:00 |
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Ross Thompson
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f055441ecf
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Improved function_radix to not printout warnings when no valid function is found.
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2022-02-01 18:03:09 -06:00 |
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Ross Thompson
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5407b72af9
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Setup the main regression test to be able to handle coremark.
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2022-02-01 17:00:11 -06:00 |
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Ross Thompson
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86bac2a083
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partial ifu cleanup.
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2022-01-31 16:08:53 -06:00 |
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Ross Thompson
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5ce8dd60c5
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Fixed modelsim warning with linux simulation.
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2022-01-31 12:57:02 -06:00 |
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Ross Thompson
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c2b2fae98d
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-01-31 12:17:37 -06:00 |
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Ross Thompson
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9cd502d0af
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Encapsulated dtim.
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2022-01-31 11:23:55 -06:00 |
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Kip Macsai-Goren
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242b27705d
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added machine info test that uses new test library
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2022-01-31 05:54:43 +00:00 |
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David Harris
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090533cfe9
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Replaced || and && with | and &
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2022-01-31 01:07:35 +00:00 |
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David Harris
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7f91170bab
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Comments in LSU code about restructuring
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2022-01-27 15:53:59 +00:00 |
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David Harris
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21bdce63ff
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Testgen working for Lab 2
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2022-01-26 18:01:51 +00:00 |
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David Harris
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07425369fc
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Renamed wallypipelinedhart to wallypipelinedcore
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2022-01-20 16:02:08 +00:00 |
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David Harris
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b63e53bbdb
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Defined rv32e and rv32emc configs
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2022-01-17 14:01:01 +00:00 |
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David Harris
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6febce0001
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Moved Dcache into bus block
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2022-01-15 00:39:07 +00:00 |
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David Harris
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2bf4676ff8
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LSU cleanup
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2022-01-14 23:55:27 +00:00 |
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David Harris
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43abf25417
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moved fp to tests
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2022-01-14 23:05:59 +00:00 |
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David Harris
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ae6792e354
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Moved fp tests from testbench to tests/fp
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2022-01-14 23:00:46 +00:00 |
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Ross Thompson
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3bec276862
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Added tim only test to regression-wally. Minor cleanup to ifu.
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2022-01-14 11:13:06 -06:00 |
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James E. Stine
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e0e30c1e9e
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Update to TestFloat for scripts so can run automatically once
TestFloat/Softfloat is compiled. Slight change to the README as well.
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2022-01-14 09:25:37 -06:00 |
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Ross Thompson
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a973681a90
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Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
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2022-01-13 22:21:43 -06:00 |
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Ross Thompson
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aad28366d7
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Partial local dtim in lsu configuration.
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2022-01-13 17:50:31 -06:00 |
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Kip Macsai-Goren
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c251144460
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Fixed PMA regions, Added passing PMA tests to regression
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2022-01-10 22:08:26 +00:00 |
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David Harris
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3a2b459439
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Merged coremark changes
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2022-01-10 05:09:28 +00:00 |
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David Harris
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39d5570d2c
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Added riscvsingle. Removed unnecessary coremark config. Added compiler flags for Coremark.
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2022-01-10 05:04:13 +00:00 |
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