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Author SHA1 Message Date
Thomas Fleming
8c97143be6 Place tlb parameters into constant header file 2021-03-05 13:35:24 -05:00
Thomas Fleming
7e11317a2d Export SATP_REGW from csrs to MMU modules 2021-03-05 01:22:53 -05:00
Noah Boorstin
f48af209c4 busybear: make CSRs only weird for us 2021-03-05 00:46:32 +00:00
Noah Boorstin
5a3ba1174e busybear: better implenetation of sim-busybear-batch 2021-03-05 00:39:03 +00:00
Ross Thompson
a662aa487c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-04 17:31:27 -06:00
Ross Thompson
264480f258 updated the function radix to look at wally signals. 2021-03-04 17:31:12 -06:00
Jarred Allen
41f682f848 Partial progress towards compressed instructions 2021-03-04 18:30:26 -05:00
Noah Boorstin
dfae278ffb busybear: make imperas tests work again 2021-03-04 22:44:49 +00:00
Katherine Parry
cfac6bf0c7 fixed various bugs 2021-03-04 22:20:39 +00:00
Katherine Parry
09564f1c77 fixed various bugs 2021-03-04 22:20:28 +00:00
Katherine Parry
a6bc39b5ad fixed various bugs 2021-03-04 22:20:23 +00:00
Katherine Parry
526e3f5996 fixed various bugs 2021-03-04 22:20:02 +00:00
Katherine Parry
1e906b36a0 fixed various bugs 2021-03-04 22:19:21 +00:00
Katherine Parry
3fb0f323b8 fixed various bugs 2021-03-04 22:18:47 +00:00
Katherine Parry
fdfc0dbf46 fixed various bugs 2021-03-04 22:18:19 +00:00
Ross Thompson
fafecb5f01 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-04 16:06:22 -06:00
Jarred Allen
106718b196 Remove rd2, working for non-compressed 2021-03-04 16:46:43 -05:00
Brett Mathis
57e484cd55 Pipelined functional units for FPU 2021-03-04 14:30:11 -06:00
Thomas Fleming
3303a013ef Merge branch 'walker' into main 2021-03-04 15:27:03 -05:00
Noah Boorstin
735c6789ea busybear: comment out instraccessfaultf for imem for now 2021-03-04 20:26:41 +00:00
Thomas Fleming
1fb50aff6b Add reference output for mmu test 2021-03-04 15:17:49 -05:00
Noah Boorstin
827dfd774b Merge branch 'main' into busybear 
Conflicts:
	wally-pipelined/src/uncore/imem.sv
 2021-03-04 20:16:03 +00:00
Ross Thompson
66e84f3a2c Merge branch 'bp' into main 
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
 2021-03-04 13:35:46 -06:00
Ross Thompson
4d14c714a7 Fixed forwarding around the 2 bit predictor. 2021-03-04 13:01:41 -06:00
Thomas Fleming
7347b3e1b7 Fix some constants in virtual memory test 2021-03-04 13:19:55 -05:00
Shreya Sanghai
246dbd05e7 fixed bugs 2021-03-04 12:59:45 -05:00
Shreya Sanghai
f0ec365117 added performance counters 2021-03-04 11:42:52 -05:00
bbracker
448cba2a5b JALR testing 2021-03-04 10:37:30 -05:00
bbracker
d98c69c4c6 changed test maker to output trace files for debug 2021-03-04 10:36:04 -05:00
Ross Thompson
52d95d415f Converted to using the BTB to predict the instruction class. 2021-03-04 09:23:35 -06:00
Teo Ene
554d529723 Slightly modified exe2memfile.pl script 2021-03-04 07:51:25 -06:00
Teo Ene
06be82fc67 Added stop to coremark_bare testbench 2021-03-04 07:47:07 -06:00
Teo Ene
8f1584ca04 Edited assemby of bare-metal coremark to make it run 2021-03-04 07:45:40 -06:00
Teo Ene
396dc61564 Linux CoreMark and baremetal CoreMark split into two separate tests/configs 2021-03-04 07:44:33 -06:00
Teo Ene
6ebb79abe0 Linux CoreMark is operational 2021-03-04 05:58:18 -06:00
Thomas Fleming
de3f2547f4 Install dtlb in dmem 2021-03-04 03:30:06 -05:00
Thomas Fleming
1df7151fb6 Install tlb into ifu 2021-03-04 03:11:34 -05:00
Thomas Fleming
2e409f2299 Merge branch 'tlb_toy' into main 2021-03-04 02:41:11 -05:00
Thomas Fleming
5f98c932bf Move tlb into mmu directory 2021-03-04 02:39:08 -05:00
Teo Ene
f060f6cb9d Fix to 32-bit option of commit babe6ce9db 2021-03-04 01:33:34 -06:00
Teo Ene
08a7f6ec25 In the process of updating coremark.RV64I program to work with Dr. Harris's perl script. Commiting to make it easier to switch branches 2021-03-04 01:27:05 -06:00
Thomas Fleming
d9f396ee0e Merge branch 'main' into tlb_toy 2021-03-04 01:18:04 -05:00
Thomas Fleming
347275e7ee Generalize tlb module 
- number of tlb entries is now parameterized
- tlb now supports rv64i
 2021-03-04 01:13:31 -05:00
Teo Ene
6031269de8 Implemented fix disucssed with Elizabeth 2021-03-03 18:17:53 -06:00
Thomas Fleming
394051c02f Begin hardware page table walker 2021-03-03 17:13:45 -05:00
Thomas Fleming
d8ac9034b7 Create virtual memory ad-hoc test 
Test program is currently failing on ovpsim. There is no indication that ovpsim
is properly implementing virtual memory translation when satp is set accordingly.
Need to confirm whether this is a problem with ovpsim, how ovpsim is being
called, or the test itself.
 2021-03-03 17:06:37 -05:00
Teo Ene
4562c61af3 Fix to last push 2021-03-03 15:20:38 -06:00
Teo Ene
37bf3d836f Updated coremark .do file for easier debugging 2021-03-03 15:10:39 -06:00
Teo Ene
e6044b9867 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-02 17:23:44 -06:00
Teo Ene
e7f7f980b3 Updated coremark .do file for easier debugging 2021-03-02 17:23:39 -06:00