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37 Commits

Author SHA1 Message Date
Ross Thompson
717833b11a Removed all old references to the old flash card controller. 
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
 2023-07-24 15:45:57 -05:00
Ross Thompson
3eeecd2f27 Merge branch 'boot' into mergeBoot 
Merges Jacob's new sdc controller into wally.
 2023-07-21 17:43:45 -05:00
Jacob Pease
36785848a5 Working new boot process. Buildroot package for sdc. 2023-07-20 14:15:59 -05:00
Ross Thompson
626a918668 FPGA updates. 2023-06-20 11:11:34 -05:00
Ross Thompson
8242544efa Updated fpga wally wrapper to work with the ILA. 2023-06-19 12:15:48 -05:00
Ross Thompson
24b8c6c391 I think the fpga is building again, but the debugger script needs to be updated. For some reason the nets are not present despite being marked debug. 2023-06-16 17:00:27 -05:00
Ross Thompson
4bee446cad Vivado requires an intermediate wrapper file for parameterization. 2023-06-16 16:30:14 -05:00
Ross Thompson
2f35bec970 FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization. 2023-06-16 15:40:13 -05:00
Ross Thompson
fad0366d26 Adding in the ILA to the arty a7. 2023-04-17 14:54:10 -05:00
Ross Thompson
d2272c0620 Found and fixed the major architecture issue with the mig 7 used in the arty a7 board. 
mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock.
 2023-04-15 11:13:28 -05:00
Ross Thompson
c9445384d7 Realized we need a separate mmcm when using the mig 7 for ddr3 rather than the ddr4 mig. Go figure. 2023-04-14 18:02:16 -05:00
Ross Thompson
b015e736a0 Updated to help debut Jacob's crossbar woes. 2023-04-11 14:22:42 -05:00
Ross Thompson
6123efd5b2 Updates for arty a7. 2023-04-10 17:02:19 -05:00
Ross Thompson
2abd164d03 Fixed syntax errors in arty7 top level. 2023-04-10 16:08:40 -05:00
Ross Thompson
81fb076e9e Added more support for Arty A7 board. 2023-04-10 16:01:17 -05:00
Jacob Pease
5161fd25cc Merge branch 'main' of github.com:openhwgroup/cvw into boot 2023-02-16 17:36:26 -06:00
David Harris
99d179dd3e Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00
Jacob Pease
536039ad86 Modified makefile. Added axi protocol converter IP. 2023-01-23 19:30:29 -06:00
Jacob Pease
24d0b1c860 Added extra core signal to mark_debug.txt. Modified wally.tcl 2023-01-23 17:00:24 -06:00
Jacob Pease
204fb84708 Merge branch 'main' of github.com:openhwgroup/cvw into boot 2023-01-23 12:41:02 -06:00
Ross Thompson
442de3f5b7 Updated fpga constraints. 2023-01-20 20:16:33 -06:00
Ross Thompson
3e1a54e80a Removed SDC from repo due to copy right issue. 
Modified fpga build flow to reference it outside the repo.
 2023-01-20 14:57:06 -06:00
Jacob Pease
dcb30dcfb2 Fixed errors in uncore and included newsdc stuff in wally.tcl 2023-01-17 16:46:00 -06:00
Jacob Pease
3b7e721823 Fixed typos. Apparently `defube causes a weird vivado error. 2023-01-13 16:59:18 -06:00
Jacob Pease
47c46bc9b5 Added IPs to wally.tcl. 2023-01-13 14:36:23 -06:00
Jacob Pease
b63927b474 Connected the axi_sdc_controller with an axi crossbar. 
Added an adrdec.sv to the adrdecs.sv file for the sake of the
cache. Modified Uncore accordingly.
 2023-01-13 13:56:01 -06:00
Ross Thompson
1510c2d92f Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile. 2022-10-24 15:38:39 -05:00
Ross Thompson
c88541cf6b test. 2022-03-28 17:04:58 -05:00
David Harris
b36ace221e Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
Ross Thompson
a11597b6bd Added more debugging code for FPGA. 2021-12-17 14:40:25 -06:00
Ross Thompson
af9f97454d Cleaned up fpga synthesis script. 2021-12-13 18:26:54 -06:00
Ross Thompson
29743c5e9e Fixed two issues. 
First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly.
Second the bidir buffer for the sd card was connected backwards.
 2021-12-07 12:15:50 -06:00
Ross Thompson
c3c9c327b7 Fixed more constraint issues in fpga. 
Added back in the ILA.
Design does not work yet.  Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
 2021-12-05 15:14:18 -06:00
Ross Thompson
5b4ff4526e Fixed a bunch of fpga issues. 2021-12-03 17:47:54 -06:00
Ross Thompson
96fb3acefd Constraints for fpga are still wrong. 2021-12-02 14:23:21 -06:00
Ross Thompson
303324d370 Added tcl commands to build the implementation. 2021-12-02 10:17:30 -06:00
Ross Thompson
e94fb2aaec Got fpga synthesis running from scripts. 2021-12-01 16:59:04 -06:00