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504 Commits

Author SHA1 Message Date
David Harris
10549b7787 Completed basic tests of svnapot and svpbmt 2023-08-28 06:57:35 -07:00
David Harris
847c0dd099
Merge pull request #393 from ross144/main 
Implemented and tested CBOZ instruction
 2023-08-24 19:17:38 -07:00
David Harris
d12be1faac
Merge pull request #394 from harshinisrinath1001/main 
Improved testing of csri with priv.S!
 2023-08-24 19:16:50 -07:00
harshinisrinath
49014e61bc Improved testing of csri with priv.S 2023-08-24 18:39:15 -07:00
Ross Thompson
c114d3a07d Added rv32 cboz test. 2023-08-24 17:02:53 -05:00
Ross Thompson
fbcf6be06d Now have CBOZ instructions working! 2023-08-24 16:47:35 -05:00
Ross Thompson
92302331b7 Oups forgot to include the 32-bit cbom test in previous commit. 2023-08-24 09:04:41 -05:00
David Harris
38e437c724
Merge pull request #383 from ross144/main 
Adds Zicbom support for D-cache only.  I-cache not yet supported.  Tests 32 and 64 bit versions.  Please rebuild regressions wally32 and wally64.  To save rebuild time edit lines 11-12 of tests/riscof/Makefile
 2023-08-21 13:32:00 -07:00
David Harris
fa49117521
Merge pull request #381 from harshinisrinath1001/main 
Tried to improve coverage of CSRI with priv.S
 2023-08-21 13:28:39 -07:00
Ross Thompson
168ef0ab53 Have a working 32 bit cbom test! 2023-08-21 13:46:09 -05:00
Ross Thompson
6ffbdaac0a Working CBO tests for 64 bit! 2023-08-21 12:55:07 -05:00
Ross Thompson
34a8c042b7 Made a bunch of progress towards getting cbo instructions tested. 2023-08-21 11:46:21 -05:00
harshinisrinath
37bfb5998f cleared stimer interrupt 2023-08-20 15:42:27 -07:00
harshinisrinath
fce2023aa8 tried to improve testing of csri in privileged module 2023-08-20 15:40:02 -07:00
David Harris
36a825c43b Improved CSRU coverage with priv.S 2023-08-20 12:49:31 -07:00
harshinisrinath
2c2c117201 wrote testcase to write into FSCR 2023-08-20 12:10:08 -07:00
Ross Thompson
6337aab757 Fixed issue when with flush miss. 2023-08-18 16:36:13 -05:00
Ross Thompson
e3bb0d2820 Now we have invalidate, clean, and flush working. 2023-08-18 16:32:22 -05:00
Ross Thompson
b9af790b81 Added cbom test to custom. Needs to be moved to wally-riscv-arch-tests. 2023-08-18 15:59:39 -05:00
harshinisrinath
15dbbef9ad Fixed bug and tried to reset menvcfg to improve testing of csri in priv. 2023-07-30 16:40:06 -07:00
harshinisrinath
24792d82e9 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-07-23 11:59:43 -07:00
Ross Thompson
3eeecd2f27 Merge branch 'boot' into mergeBoot 
Merges Jacob's new sdc controller into wally.
 2023-07-21 17:43:45 -05:00
Jacob Pease
36785848a5 Working new boot process. Buildroot package for sdc. 2023-07-20 14:15:59 -05:00
Jacob Pease
142ec857ed Modified bootloader to access GUID partitions. SDC interrupt to PLIC. 
Since writing an SD card image generation script, the bootloader
needed to be altered to access individual binaries from specific
partitions. A new file, gpt.c with it's header gpt.h, have been added
to the bootloader to facilitate this.

The SDC has been added to the device tree for the VCU108
board. Additionally the SDC interrupt signal was added to the PLIC
node in the device tree. The PLIC itself  was modified to accept the
SDC interrupt signal.
 2023-07-14 13:36:44 -05:00
harshinisrinath
cba045b53c Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-07-13 13:00:58 -07:00
Kevin Kim
7e185a2f0d fixed bug in testvector extract script 
-old script skips first 2 lines in rv32m case, new script only skips first line
- prior code skipped every other line in the reference file, so it only generated half the test vectors, with half of them having the wrong answer
- prior code also opened test vector file to be written to in "append" mode, and I changed to write mode (so that the script overwrites instead of adding to an existing file)
 2023-06-22 09:13:22 -07:00
harshinisrinath
dc6633c796 Improved testing of pmd in priv. 2023-06-16 17:13:54 -07:00
harshinisrinath
c9695e6813 Improve test coverage on ieu fw. 2023-06-16 16:09:48 -07:00
David Harris
b20363f9c2 Fixed timer interrupt testing 2023-06-09 17:20:41 -07:00
David Harris
9373ad3811 Fixed WALLY-trap test case to use menvcfg 2023-06-09 15:24:26 -07:00
David Harris
b15c5e2a51 Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare 2023-06-09 14:40:01 -07:00
Ross Thompson
f4883e31df
Merge pull request #314 from davidharrishmc/dev 
Make and FP script improvements
 2023-06-06 12:38:26 -04:00
James Stine
736ae7d749 Update fcvt tests for l.s/lu.s and s.l/s.lu that were missing 2023-06-05 11:03:59 -05:00
David Harris
c1e7332abf Fixed paths in creating division test vectors 2023-05-31 06:30:41 -07:00
David Harris
8c1bd8523a Clean up combined int/fp vector creation 2023-05-30 14:01:12 -07:00
Jacob Pease
2ad9c72acc The Vivado-RISC-V SDC works. Wally is now booting through it. 2023-05-26 15:42:33 -05:00
David Harris
e2c990f47d Increased timeout for riscof because it is so slow 2023-05-23 15:37:09 -07:00
David Harris
bdd0ab5a55 Added Zifencei ISA to tests where necessary to support new compiler 2023-05-16 11:18:27 -07:00
David Harris
f5db0a714d Added Zicsr and zifencei to RVTEST_ISA in custom tests where necessary to make them compile 2023-05-14 06:58:29 -07:00
David Harris
402395b126 Fixed riscof scripts that were removing zicsr from compiler misa 2023-05-14 04:19:08 -07:00
David Harris
c6a6269404 Defined empty RVMODEL interrupt macros to make riscof warnings go away 2023-05-14 03:36:28 -07:00
Kevin Thomas
968c228fcc Comment tlbGBL more discriptively 
Reduce redundant instructions
 2023-05-04 19:13:47 -05:00
David Harris
2b9b2f21df
Merge branch 'main' into main 2023-04-28 07:51:32 -07:00
Liam Chalk
8ef9e77e00
Merge branch 'main' into main 2023-04-27 21:49:01 -07:00
Kevin Wan
c0cbd0fd2a added tests for pmppriority module 2023-04-27 16:12:43 -07:00
David Harris
c04f636952
Update tlbASID.S 
fixed comment about restoring ASID to 0
 2023-04-27 14:32:57 -07:00
Noah Limpert
26cb639f89 complete camline coverage on IFU and LSU 2023-04-27 14:26:10 -07:00
Liam
6803347a49 Pmpadrdecs test cases changing AdrMode to 2 or 3 
Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] writing values to pmpcfg0 to change AdrMode to 2 or 3
Also exclusion for pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1 in pmpadrdec.sv
 2023-04-27 12:23:35 -07:00
Alexa Wright
667c54c129
Merge branch 'openhwgroup:main' into main 2023-04-26 16:26:30 -07:00
Alexa Wright
55a74fd315 Excluded and added coverage for WFI test case. 2023-04-25 17:06:57 -07:00